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module VGADataBuffer(
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module VGADataBuffer(
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CLK_50MHZ, MASTER_RST,
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CLK_50MHZ, MASTER_RST,
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VGA_RAM_DATA, VGA_RAM_ADDR, VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
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VGA_RAM_DATA, VGA_RAM_ADDR, VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
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VGA_RAM_ACCESS_OK,
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VGA_RAM_ACCESS_OK,
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ADC_RAM_DATA, ADC_RAM_ADDR, ADC_RAM_CLK,
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ADC_RAM_DATA, ADC_RAM_ADDR, ADC_RAM_CLK,
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TIME_BASE,
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TIME_BASE
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TRIG_ADDR, VGA_WRITE_DONE
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);
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);
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//==================================================================//
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//==================================================================//
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// VARIABLE DEFINITIONS //
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// VARIABLE DEFINITIONS //
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//==================================================================//
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//==================================================================//
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//----------------------//
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//----------------------//
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output[15:0] VGA_RAM_DATA;
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output[15:0] VGA_RAM_DATA;
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output[17:0] VGA_RAM_ADDR;
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output[17:0] VGA_RAM_ADDR;
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output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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output VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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input VGA_RAM_ACCESS_OK;
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input VGA_RAM_ACCESS_OK;
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input[7:0] ADC_RAM_DATA;
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input[8:0] ADC_RAM_DATA;
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output[10:0] ADC_RAM_ADDR;
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output[10:0] ADC_RAM_ADDR;
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output ADC_RAM_CLK;
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output ADC_RAM_CLK;
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input[5:0] TIME_BASE;
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input[5:0] TIME_BASE;
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output VGA_WRITE_DONE;
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input[10:0] TRIG_ADDR;
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//----------------------//
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//----------------------//
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// WIRES / NODES //
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// WIRES / NODES //
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//----------------------//
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//----------------------//
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wire CLK_50MHZ; // System wide clock
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wire CLK_50MHZ; // System wide clock
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wire MASTER_RST; // System wide reset
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wire MASTER_RST; // System wide reset
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wire[15:0] VGA_RAM_DATA;
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wire[15:0] VGA_RAM_DATA;
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reg[17:0] VGA_RAM_ADDR;
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reg[17:0] VGA_RAM_ADDR;
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reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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reg VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS;
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wire VGA_RAM_ACCESS_OK;
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wire VGA_RAM_ACCESS_OK;
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wire[7:0] ADC_RAM_DATA;
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wire[8:0] ADC_RAM_DATA;
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reg[10:0] ADC_RAM_ADDR;
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reg[10:0] ADC_RAM_ADDR;
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wire ADC_RAM_CLK;
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wire ADC_RAM_CLK;
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wire[5:0] TIME_BASE;
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wire[5:0] TIME_BASE;
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reg VGA_WRITE_DONE;
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wire[10:0] TRIG_ADDR;
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//----------------------//
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//----------------------//
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// REGISTERS //
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// REGISTERS //
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//----------------------//
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//----------------------//
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end else begin
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end else begin
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hcnt <= 10'b0;
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hcnt <= 10'b0;
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end
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end
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end
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end
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/* VGA_WRITE_DONE -> BASED ON hcnt */
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always @ (hcnt) begin
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if(hcnt == 10'd640)
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VGA_WRITE_DONE = 1'b1;
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else
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VGA_WRITE_DONE = 1'b0;
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end
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/* TRIG_ADDR modified */
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always @ (TRIG_ADDR) begin
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if(TRIG_ADDR < 10'd320)
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TRIG_ADDR_buffered = (11'd2047 - 10'd320) - TRIG_ADDR;
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else
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TRIG_ADDR_buffered = TRIG_ADDR;
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end
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always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
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always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
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if(MASTER_RST == 1'b1) begin
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if(MASTER_RST == 1'b1) begin
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ADC_RAM_ADDR <= 11'b0;
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ADC_RAM_ADDR <= 11'b0;
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end else if(VGA_RAM_ACCESS_OK) begin
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end else if(VGA_RAM_ACCESS_OK) begin
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if((hcnt == 10'd640) || !(vcnt == 5'd24))
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if((hcnt == 10'd640) || !(vcnt == 5'd24))
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ADC_RAM_ADDR <= ADC_RAM_ADDR;
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ADC_RAM_ADDR <= ADC_RAM_ADDR;
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else
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else
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ADC_RAM_ADDR <= ADC_RAM_ADDR + 1'b1;
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ADC_RAM_ADDR <= ADC_RAM_ADDR + 1'b1;
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end else begin
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end else begin
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ADC_RAM_ADDR <= TRIG_ADDR_buffered;
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ADC_RAM_ADDR <= 11'd1727;
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end
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end
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end
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end
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reg[7:0] TESTING_CNT;
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reg[7:0] TESTING_CNT;
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always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
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always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
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