| Line 62... |
Line 62... |
// Load pending / target
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// Load pending / target
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input load_pending_i /*verilator public*/,
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input load_pending_i /*verilator public*/,
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input [4:0] rd_load_i /*verilator public*/,
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input [4:0] rd_load_i /*verilator public*/,
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// Multiplier status
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// Multiplier status
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input mult_lo_ex_i /*verilator public*/,
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input mult_ex_i /*verilator public*/,
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input mult_hi_ex_i /*verilator public*/,
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input mult_lo_wb_i /*verilator public*/,
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input mult_hi_wb_i /*verilator public*/,
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// Multiplier result
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input [63:0] result_mult_i /*verilator public*/,
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// Result (EXEC)
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// Result (EXEC)
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input [31:0] result_ex_i /*verilator public*/,
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input [31:0] result_ex_i /*verilator public*/,
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// Result (WB)
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// Result (WB)
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| Line 122... |
Line 116... |
// RA from PC-4 (exec)
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// RA from PC-4 (exec)
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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else if (ra_i == rd_ex_i)
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else if (ra_i == rd_ex_i)
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begin
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begin
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// Multiplier has one cycle latency, stall if needed now
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// Multiplier has one cycle latency, stall if needed now
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if (mult_lo_ex_i | mult_hi_wb_i)
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if (mult_ex_i)
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stall_o = 1'b1;
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stall_o = 1'b1;
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else
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else
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begin
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begin
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result_ra_o = result_ex_i;
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result_ra_o = result_ex_i;
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resolved_o = 1'b1;
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resolved_o = 1'b1;
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| Line 138... |
Line 132... |
//---------------------------------------------------------------
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//---------------------------------------------------------------
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// RA from PC-8 (writeback)
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// RA from PC-8 (writeback)
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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else if (ra_i == rd_wb_i)
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else if (ra_i == rd_wb_i)
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begin
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begin
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if (mult_hi_wb_i)
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result_ra_o = result_mult_i[63:32];
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else if (mult_lo_wb_i)
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result_ra_o = result_mult_i[31:0];
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else
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result_ra_o = result_wb_i;
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result_ra_o = result_wb_i;
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resolved_o = 1'b1;
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resolved_o = 1'b1;
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`ifdef CONF_CORE_DEBUG
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`ifdef CONF_CORE_DEBUG
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$display(" rA[%d] forwarded 0x%08x (PC-8)", ra_i, result_ra_o);
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$display(" rA[%d] forwarded 0x%08x (PC-8)", ra_i, result_ra_o);
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| Line 177... |
Line 166... |
// RB from PC-4 (exec)
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// RB from PC-4 (exec)
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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else if (rb_i == rd_ex_i)
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else if (rb_i == rd_ex_i)
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begin
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begin
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// Multiplier has one cycle latency, stall if needed now
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// Multiplier has one cycle latency, stall if needed now
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if (mult_lo_ex_i | mult_hi_wb_i)
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if (mult_ex_i)
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stall_o = 1'b1;
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stall_o = 1'b1;
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else
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else
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begin
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begin
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result_rb_o = result_ex_i;
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result_rb_o = result_ex_i;
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resolved_o = 1'b1;
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resolved_o = 1'b1;
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| Line 194... |
Line 183... |
//---------------------------------------------------------------
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//---------------------------------------------------------------
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// RB from PC-8 (writeback)
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// RB from PC-8 (writeback)
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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else if (rb_i == rd_wb_i)
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else if (rb_i == rd_wb_i)
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begin
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begin
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if (mult_hi_wb_i)
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result_rb_o = result_mult_i[63:32];
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else if (mult_lo_wb_i)
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result_rb_o = result_mult_i[31:0];
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else
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result_rb_o = result_wb_i;
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result_rb_o = result_wb_i;
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resolved_o = 1'b1;
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resolved_o = 1'b1;
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`ifdef CONF_CORE_DEBUG
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`ifdef CONF_CORE_DEBUG
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