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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_noicache.v] - Diff between revs 36 and 37

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//               Email: admin@ultra-embedded.com
//               Email: admin@ultra-embedded.com
//
//
//                       License: LGPL
//                       License: LGPL
//-----------------------------------------------------------------
//-----------------------------------------------------------------
//
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
//
// This source file may be used and distributed without         
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
// the original copyright notice and the associated disclaimer. 
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    // Invalidate (not used)
    // Invalidate (not used)
    input                       invalidate_i /*verilator public*/,
    input                       invalidate_i /*verilator public*/,
 
 
    // Memory interface
    // Memory interface
    output reg [31:0]           wbm_addr_o /*verilator public*/,
    output [31:0]               wbm_addr_o /*verilator public*/,
    input [31:0]                wbm_dat_i /*verilator public*/,
    input [31:0]                wbm_dat_i /*verilator public*/,
    output [2:0]                wbm_cti_o /*verilator public*/,
    output [2:0]                wbm_cti_o /*verilator public*/,
    output reg                  wbm_cyc_o /*verilator public*/,
    output                      wbm_cyc_o /*verilator public*/,
    output reg                  wbm_stb_o /*verilator public*/,
    output                      wbm_stb_o /*verilator public*/,
    input                       wbm_stall_i/*verilator public*/,
    input                       wbm_stall_i/*verilator public*/,
    input                       wbm_ack_i/*verilator public*/
    input                       wbm_ack_i/*verilator public*/
);
);
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
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//-----------------------------------------------------------------
//-----------------------------------------------------------------
 
 
// Current state
// Current state
parameter STATE_CHECK       = 0;
parameter STATE_CHECK       = 0;
parameter STATE_FETCH       = 1;
parameter STATE_FETCH       = 1;
reg                        state;
reg                     state_q;
 
 
reg                        ignore_resp;
reg                     drop_resp_q;
 
 
assign valid_o              = wbm_ack_i & ~ignore_resp & ~rd_i;
wire                    mem_fetch_w = (state_q == STATE_CHECK);
assign instruction_o        = wbm_dat_i;
wire                    mem_valid_w;
 
wire                    mem_final_w;
 
 
 
//-----------------------------------------------------------------
 
// Fetch unit
 
//-----------------------------------------------------------------
 
altor32_wb_fetch
 
u_wb
 
(
 
    .clk_i(clk_i),
 
    .rst_i(rst_i),
 
 
 
    .fetch_i(mem_fetch_w),
 
    .burst_i(1'b0),
 
    .address_i(pc_i),
 
 
 
    .resp_addr_o(/* not used */),
 
    .data_o(instruction_o),
 
    .valid_o(mem_valid_w),
 
    .final_o(mem_final_w),
 
 
 
    .wbm_addr_o(wbm_addr_o),
 
    .wbm_dat_i(wbm_dat_i),
 
    .wbm_cti_o(wbm_cti_o),
 
    .wbm_cyc_o(wbm_cyc_o),
 
    .wbm_stb_o(wbm_stb_o),
 
    .wbm_stall_i(wbm_stall_i),
 
    .wbm_ack_i(wbm_ack_i)
 
);
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Control logic
// Control logic
//-----------------------------------------------------------------
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
always @ (posedge rst_i or posedge clk_i )
begin
begin
   if (rst_i == 1'b1)
   if (rst_i == 1'b1)
   begin
   begin
        wbm_addr_o      <= 32'h00000000;
        drop_resp_q <= 1'b0;
        wbm_stb_o       <= 1'b0;
        state_q     <= STATE_CHECK;
        wbm_cyc_o       <= 1'b0;
 
        ignore_resp     <= 1'b0;
 
        state           <= STATE_CHECK;
 
   end
   end
   else
   else
   begin
   begin
 
        case (state_q)
        if (~wbm_stall_i)
 
            wbm_stb_o    <= 1'b0;
 
 
 
        case (state)
 
 
 
            //-----------------------------------------
            //-----------------------------------------
            // CHECK - check cache for hit or miss
            // CHECK - Accept read request
            //-----------------------------------------
            //-----------------------------------------
            STATE_CHECK :
            STATE_CHECK :
            begin
            begin
                // Start fetch from memory
                drop_resp_q         <= 1'b0;
                wbm_addr_o  <= pc_i;
                state_q             <= STATE_FETCH;
                wbm_stb_o   <= 1'b1;
 
                wbm_cyc_o   <= 1'b1;
 
                ignore_resp <= 1'b0;
 
                state       <= STATE_FETCH;
 
            end
            end
            //-----------------------------------------
            //-----------------------------------------
            // FETCH - Fetch row from memory
            // FETCH - Wait for read response
            //-----------------------------------------
            //-----------------------------------------
            STATE_FETCH :
            STATE_FETCH :
            begin
            begin
                // Read whilst waiting for previous response?        
                // Read whilst waiting for previous response?        
                if (rd_i)
                if (rd_i)
                    ignore_resp <= 1'b1;
                    drop_resp_q     <= 1'b1;
 
 
                // Data ready from memory?
                // Data ready from memory?
                if (wbm_ack_i)
                if (mem_final_w)
                begin
                    state_q         <= STATE_CHECK;
                    wbm_cyc_o   <= 1'b0;
 
                    state       <= STATE_CHECK;
 
                end
 
            end
            end
 
 
            default:
            default:
                ;
                ;
           endcase
           endcase
   end
   end
end
end
 
 
assign wbm_cti_o        = 3'b111;
assign valid_o              = mem_valid_w & ~drop_resp_q & ~rd_i;
 
assign instruction_o        = wbm_dat_i;
 
 
endmodule
endmodule
 
 
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