| Line 49... |
Line 49... |
input rst_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input wr_i /*verilator public*/,
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input wr_i /*verilator public*/,
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input [4:0] rs_i /*verilator public*/,
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input [4:0] rs_i /*verilator public*/,
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input [4:0] rt_i /*verilator public*/,
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input [4:0] rt_i /*verilator public*/,
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input [4:0] rd_i /*verilator public*/,
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input [4:0] rd_i /*verilator public*/,
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output [31:0] reg_rs_o /*verilator public*/,
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output reg [31:0] reg_rs_o /*verilator public*/,
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output [31:0] reg_rt_o /*verilator public*/,
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output reg [31:0] reg_rt_o /*verilator public*/,
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input [31:0] reg_rd_i /*verilator public*/
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input [31:0] reg_rd_i /*verilator public*/
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);
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);
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|
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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| Line 96... |
Line 96... |
reg [31:0] reg_r28;
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reg [31:0] reg_r28;
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reg [31:0] reg_r29;
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reg [31:0] reg_r29;
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reg [31:0] reg_r30;
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reg [31:0] reg_r30;
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reg [31:0] reg_r31;
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reg [31:0] reg_r31;
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|
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reg [31:0] reg_rs_o;
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reg [31:0] reg_rt_o;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Register File (for simulation)
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// Register File (for simulation)
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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|
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// Synchronous register write back
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// Synchronous register write back
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