| Line 8... |
Line 8... |
// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2014 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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| Line 46... |
Line 46... |
module altor32_regfile_sim
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module altor32_regfile_sim
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(
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(
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input clk_i /*verilator public*/,
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input clk_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input wr_i /*verilator public*/,
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input wr_i /*verilator public*/,
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input [4:0] rs_i /*verilator public*/,
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input [4:0] ra_i /*verilator public*/,
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input [4:0] rt_i /*verilator public*/,
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input [4:0] rb_i /*verilator public*/,
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input [4:0] rd_i /*verilator public*/,
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input [4:0] rd_i /*verilator public*/,
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output reg [31:0] reg_rs_o /*verilator public*/,
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output reg [31:0] reg_ra_o /*verilator public*/,
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output reg [31:0] reg_rt_o /*verilator public*/,
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output reg [31:0] reg_rb_o /*verilator public*/,
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input [31:0] reg_rd_i /*verilator public*/
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input [31:0] reg_rd_i /*verilator public*/
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);
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);
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|
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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| Line 215... |
Line 215... |
if (SUPPORT_32REGS == "ENABLED")
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if (SUPPORT_32REGS == "ENABLED")
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begin
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begin
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// Asynchronous Register read (Rs & Rd)
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// Asynchronous Register read (Rs & Rd)
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always @ *
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always @ *
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begin
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begin
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case (rs_i)
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case (ra_i)
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5'b00000 :
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5'b00000 :
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reg_rs_o = 32'h00000000;
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reg_ra_o = 32'h00000000;
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5'b00001 :
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5'b00001 :
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reg_rs_o = reg_r1_sp;
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reg_ra_o = reg_r1_sp;
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5'b00010 :
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5'b00010 :
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reg_rs_o = reg_r2_fp;
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reg_ra_o = reg_r2_fp;
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5'b00011 :
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5'b00011 :
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reg_rs_o = reg_r3;
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reg_ra_o = reg_r3;
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5'b00100 :
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5'b00100 :
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reg_rs_o = reg_r4;
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reg_ra_o = reg_r4;
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5'b00101 :
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5'b00101 :
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reg_rs_o = reg_r5;
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reg_ra_o = reg_r5;
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5'b00110 :
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5'b00110 :
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reg_rs_o = reg_r6;
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reg_ra_o = reg_r6;
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5'b00111 :
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5'b00111 :
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reg_rs_o = reg_r7;
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reg_ra_o = reg_r7;
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5'b01000 :
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5'b01000 :
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reg_rs_o = reg_r8;
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reg_ra_o = reg_r8;
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5'b01001 :
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5'b01001 :
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reg_rs_o = reg_r9_lr;
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reg_ra_o = reg_r9_lr;
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5'b01010 :
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5'b01010 :
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reg_rs_o = reg_r10;
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reg_ra_o = reg_r10;
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5'b01011 :
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5'b01011 :
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reg_rs_o = reg_r11;
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reg_ra_o = reg_r11;
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5'b01100 :
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5'b01100 :
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reg_rs_o = reg_r12;
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reg_ra_o = reg_r12;
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5'b01101 :
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5'b01101 :
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reg_rs_o = reg_r13;
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reg_ra_o = reg_r13;
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5'b01110 :
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5'b01110 :
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reg_rs_o = reg_r14;
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reg_ra_o = reg_r14;
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5'b01111 :
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5'b01111 :
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reg_rs_o = reg_r15;
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reg_ra_o = reg_r15;
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5'b10000 :
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5'b10000 :
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reg_rs_o = reg_r16;
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reg_ra_o = reg_r16;
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5'b10001 :
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5'b10001 :
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reg_rs_o = reg_r17;
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reg_ra_o = reg_r17;
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5'b10010 :
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5'b10010 :
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reg_rs_o = reg_r18;
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reg_ra_o = reg_r18;
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5'b10011 :
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5'b10011 :
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reg_rs_o = reg_r19;
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reg_ra_o = reg_r19;
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5'b10100 :
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5'b10100 :
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reg_rs_o = reg_r20;
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reg_ra_o = reg_r20;
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5'b10101 :
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5'b10101 :
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reg_rs_o = reg_r21;
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reg_ra_o = reg_r21;
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5'b10110 :
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5'b10110 :
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reg_rs_o = reg_r22;
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reg_ra_o = reg_r22;
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5'b10111 :
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5'b10111 :
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reg_rs_o = reg_r23;
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reg_ra_o = reg_r23;
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5'b11000 :
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5'b11000 :
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reg_rs_o = reg_r24;
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reg_ra_o = reg_r24;
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5'b11001 :
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5'b11001 :
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reg_rs_o = reg_r25;
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reg_ra_o = reg_r25;
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5'b11010 :
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5'b11010 :
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reg_rs_o = reg_r26;
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reg_ra_o = reg_r26;
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5'b11011 :
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5'b11011 :
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reg_rs_o = reg_r27;
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reg_ra_o = reg_r27;
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5'b11100 :
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5'b11100 :
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reg_rs_o = reg_r28;
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reg_ra_o = reg_r28;
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5'b11101 :
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5'b11101 :
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reg_rs_o = reg_r29;
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reg_ra_o = reg_r29;
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5'b11110 :
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5'b11110 :
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reg_rs_o = reg_r30;
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reg_ra_o = reg_r30;
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5'b11111 :
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5'b11111 :
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reg_rs_o = reg_r31;
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reg_ra_o = reg_r31;
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default :
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default :
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reg_rs_o = 32'h00000000;
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reg_ra_o = 32'h00000000;
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endcase
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endcase
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|
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case (rt_i)
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case (rb_i)
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5'b00000 :
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5'b00000 :
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reg_rt_o = 32'h00000000;
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reg_rb_o = 32'h00000000;
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5'b00001 :
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5'b00001 :
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reg_rt_o = reg_r1_sp;
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reg_rb_o = reg_r1_sp;
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5'b00010 :
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5'b00010 :
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reg_rt_o = reg_r2_fp;
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reg_rb_o = reg_r2_fp;
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5'b00011 :
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5'b00011 :
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reg_rt_o = reg_r3;
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reg_rb_o = reg_r3;
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5'b00100 :
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5'b00100 :
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reg_rt_o = reg_r4;
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reg_rb_o = reg_r4;
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5'b00101 :
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5'b00101 :
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reg_rt_o = reg_r5;
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reg_rb_o = reg_r5;
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5'b00110 :
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5'b00110 :
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reg_rt_o = reg_r6;
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reg_rb_o = reg_r6;
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5'b00111 :
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5'b00111 :
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reg_rt_o = reg_r7;
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reg_rb_o = reg_r7;
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5'b01000 :
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5'b01000 :
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reg_rt_o = reg_r8;
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reg_rb_o = reg_r8;
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5'b01001 :
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5'b01001 :
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reg_rt_o = reg_r9_lr;
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reg_rb_o = reg_r9_lr;
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5'b01010 :
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5'b01010 :
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reg_rt_o = reg_r10;
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reg_rb_o = reg_r10;
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5'b01011 :
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5'b01011 :
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reg_rt_o = reg_r11;
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reg_rb_o = reg_r11;
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5'b01100 :
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5'b01100 :
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reg_rt_o = reg_r12;
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reg_rb_o = reg_r12;
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5'b01101 :
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5'b01101 :
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reg_rt_o = reg_r13;
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reg_rb_o = reg_r13;
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5'b01110 :
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5'b01110 :
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reg_rt_o = reg_r14;
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reg_rb_o = reg_r14;
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5'b01111 :
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5'b01111 :
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reg_rt_o = reg_r15;
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reg_rb_o = reg_r15;
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5'b10000 :
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5'b10000 :
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reg_rt_o = reg_r16;
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reg_rb_o = reg_r16;
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5'b10001 :
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5'b10001 :
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reg_rt_o = reg_r17;
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reg_rb_o = reg_r17;
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5'b10010 :
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5'b10010 :
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reg_rt_o = reg_r18;
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reg_rb_o = reg_r18;
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5'b10011 :
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5'b10011 :
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reg_rt_o = reg_r19;
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reg_rb_o = reg_r19;
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5'b10100 :
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5'b10100 :
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reg_rt_o = reg_r20;
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reg_rb_o = reg_r20;
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5'b10101 :
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5'b10101 :
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reg_rt_o = reg_r21;
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reg_rb_o = reg_r21;
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5'b10110 :
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5'b10110 :
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reg_rt_o = reg_r22;
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reg_rb_o = reg_r22;
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5'b10111 :
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5'b10111 :
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reg_rt_o = reg_r23;
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reg_rb_o = reg_r23;
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5'b11000 :
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5'b11000 :
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reg_rt_o = reg_r24;
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reg_rb_o = reg_r24;
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5'b11001 :
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5'b11001 :
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reg_rt_o = reg_r25;
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reg_rb_o = reg_r25;
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5'b11010 :
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5'b11010 :
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reg_rt_o = reg_r26;
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reg_rb_o = reg_r26;
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5'b11011 :
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5'b11011 :
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reg_rt_o = reg_r27;
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reg_rb_o = reg_r27;
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5'b11100 :
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5'b11100 :
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reg_rt_o = reg_r28;
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reg_rb_o = reg_r28;
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5'b11101 :
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5'b11101 :
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reg_rt_o = reg_r29;
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reg_rb_o = reg_r29;
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5'b11110 :
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5'b11110 :
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reg_rt_o = reg_r30;
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reg_rb_o = reg_r30;
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5'b11111 :
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5'b11111 :
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reg_rt_o = reg_r31;
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reg_rb_o = reg_r31;
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default :
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default :
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reg_rt_o = 32'h00000000;
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reg_rb_o = 32'h00000000;
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endcase
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endcase
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end
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end
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end
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end
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else
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else
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begin
|
begin
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// Asynchronous Register read (Rs & Rd)
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// Asynchronous Register read (Rs & Rd)
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always @ *
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always @ *
|
begin
|
begin
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case (rs_i)
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case (ra_i)
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5'b00000 :
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5'b00000 :
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reg_rs_o = 32'h00000000;
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reg_ra_o = 32'h00000000;
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5'b00001 :
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5'b00001 :
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reg_rs_o = reg_r1_sp;
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reg_ra_o = reg_r1_sp;
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5'b00010 :
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5'b00010 :
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reg_rs_o = reg_r2_fp;
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reg_ra_o = reg_r2_fp;
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5'b00011 :
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5'b00011 :
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reg_rs_o = reg_r3;
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reg_ra_o = reg_r3;
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5'b00100 :
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5'b00100 :
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reg_rs_o = reg_r4;
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reg_ra_o = reg_r4;
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5'b00101 :
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5'b00101 :
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reg_rs_o = reg_r5;
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reg_ra_o = reg_r5;
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5'b00110 :
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5'b00110 :
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reg_rs_o = reg_r6;
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reg_ra_o = reg_r6;
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5'b00111 :
|
5'b00111 :
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reg_rs_o = reg_r7;
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reg_ra_o = reg_r7;
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5'b01000 :
|
5'b01000 :
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reg_rs_o = reg_r8;
|
reg_ra_o = reg_r8;
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5'b01001 :
|
5'b01001 :
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reg_rs_o = reg_r9_lr;
|
reg_ra_o = reg_r9_lr;
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5'b01010 :
|
5'b01010 :
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reg_rs_o = reg_r10;
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reg_ra_o = reg_r10;
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5'b01011 :
|
5'b01011 :
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reg_rs_o = reg_r11;
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reg_ra_o = reg_r11;
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5'b01100 :
|
5'b01100 :
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reg_rs_o = reg_r12;
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reg_ra_o = reg_r12;
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5'b01101 :
|
5'b01101 :
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reg_rs_o = reg_r13;
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reg_ra_o = reg_r13;
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5'b01110 :
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5'b01110 :
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reg_rs_o = reg_r14;
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reg_ra_o = reg_r14;
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5'b01111 :
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5'b01111 :
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reg_rs_o = reg_r15;
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reg_ra_o = reg_r15;
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default :
|
default :
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reg_rs_o = 32'h00000000;
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reg_ra_o = 32'h00000000;
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endcase
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endcase
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|
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case (rt_i)
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case (rb_i)
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5'b00000 :
|
5'b00000 :
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reg_rt_o = 32'h00000000;
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reg_rb_o = 32'h00000000;
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5'b00001 :
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5'b00001 :
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reg_rt_o = reg_r1_sp;
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reg_rb_o = reg_r1_sp;
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5'b00010 :
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5'b00010 :
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reg_rt_o = reg_r2_fp;
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reg_rb_o = reg_r2_fp;
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5'b00011 :
|
5'b00011 :
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reg_rt_o = reg_r3;
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reg_rb_o = reg_r3;
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5'b00100 :
|
5'b00100 :
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reg_rt_o = reg_r4;
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reg_rb_o = reg_r4;
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5'b00101 :
|
5'b00101 :
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reg_rt_o = reg_r5;
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reg_rb_o = reg_r5;
|
5'b00110 :
|
5'b00110 :
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reg_rt_o = reg_r6;
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reg_rb_o = reg_r6;
|
5'b00111 :
|
5'b00111 :
|
reg_rt_o = reg_r7;
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reg_rb_o = reg_r7;
|
5'b01000 :
|
5'b01000 :
|
reg_rt_o = reg_r8;
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reg_rb_o = reg_r8;
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5'b01001 :
|
5'b01001 :
|
reg_rt_o = reg_r9_lr;
|
reg_rb_o = reg_r9_lr;
|
5'b01010 :
|
5'b01010 :
|
reg_rt_o = reg_r10;
|
reg_rb_o = reg_r10;
|
5'b01011 :
|
5'b01011 :
|
reg_rt_o = reg_r11;
|
reg_rb_o = reg_r11;
|
5'b01100 :
|
5'b01100 :
|
reg_rt_o = reg_r12;
|
reg_rb_o = reg_r12;
|
5'b01101 :
|
5'b01101 :
|
reg_rt_o = reg_r13;
|
reg_rb_o = reg_r13;
|
5'b01110 :
|
5'b01110 :
|
reg_rt_o = reg_r14;
|
reg_rb_o = reg_r14;
|
5'b01111 :
|
5'b01111 :
|
reg_rt_o = reg_r15;
|
reg_rb_o = reg_r15;
|
default :
|
default :
|
reg_rt_o = 32'h00000000;
|
reg_rb_o = 32'h00000000;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
