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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2014 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers
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// Registers
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Register address
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// Register address
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reg [4:0] r_w_rd;
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reg [4:0] rd_q;
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// Register writeback value
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// Register writeback value
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reg [31:0] r_result;
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reg [31:0] result_q;
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reg [7:0] r_opcode;
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reg [7:0] opcode_q;
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// Register writeback enable
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// Register writeback enable
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reg r_w_write_rd;
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reg write_rd_q;
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Writeback
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// Writeback
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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always @ (posedge clk_i or posedge rst_i)
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always @ (posedge clk_i or posedge rst_i)
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begin
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begin
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if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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begin
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begin
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r_w_write_rd <= 1'b1;
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write_rd_q <= 1'b1;
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r_result <= 32'h00000000;
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result_q <= 32'h00000000;
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r_w_rd <= 5'b00000;
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rd_q <= 5'b00000;
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r_opcode <= 8'b0;
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opcode_q <= 8'b0;
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end
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end
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else
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else
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begin
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begin
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r_w_write_rd <= 1'b0;
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rd_q <= rd_i;
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result_q <= alu_result_i;
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r_w_rd <= rd_i;
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opcode_q <= {2'b00,opcode_i[31:26]};
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r_result <= alu_result_i;
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r_opcode <= {2'b00,opcode_i[31:26]};
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// Register writeback required?
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// Register writeback required?
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if (rd_i != 5'b00000)
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if (rd_i != 5'b00000)
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r_w_write_rd <= 1'b1;
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write_rd_q <= 1'b1;
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else
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write_rd_q <= 1'b0;
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end
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end
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end
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end
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Load result resolve
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// Load result resolve
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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wire load_insn;
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wire load_inst_w;
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wire [31:0] load_result;
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wire [31:0] load_result_w;
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altor32_lfu
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altor32_lfu
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u_lfu
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u_lfu
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(
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(
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// Opcode
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// Opcode
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.opcode_i(r_opcode),
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.opcode_i(opcode_q),
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// Memory load result
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// Memory load result
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.mem_result_i(mem_result_i),
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.mem_result_i(mem_result_i),
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.mem_offset_i(mem_offset_i),
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.mem_offset_i(mem_offset_i),
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// Result
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// Result
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.load_result_o(load_result),
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.load_result_o(load_result_w),
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.load_insn_o(load_insn)
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.load_insn_o(load_inst_w)
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);
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);
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Assignments
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// Assignments
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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assign write_enable_o = load_insn ? (r_w_write_rd & mem_ready_i) : r_w_write_rd;
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assign write_enable_o = load_inst_w ? (write_rd_q & mem_ready_i) : write_rd_q;
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assign write_data_o = load_insn ? load_result : (mult_i ? mult_result_i : r_result);
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assign write_data_o = load_inst_w ? load_result_w : (mult_i ? mult_result_i : result_q);
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assign write_addr_o = r_w_rd;
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assign write_addr_o = rd_q;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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