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[/] [altor32/] [trunk/] [rtl/] [cpu_lite/] [altor32_lite.v] - Diff between revs 37 and 39

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Rev 37 Rev 39
Line 124... Line 124... 
wire        compare_equal_w;
 
wire        compare_equal_w;
 
wire        compare_gts_w;
 
wire        compare_gts_w;
 
wire        compare_gt_w;
 
wire        compare_gt_w;
 
wire        compare_lts_w;
 
wire        compare_lts_w;
 
wire        compare_lt_w;
 
wire        compare_lt_w;
 
wire        alu_flag_update;
 
wire        alu_flag_update_w;
 
 
 
 
 
// ALU operation selection
 
// ALU operation selection
 
reg [3:0]   ex_alu_func_q;
 
reg [3:0]   ex_alu_func_q;
 
 
 
 
 
// Delayed NMI
 
// Delayed NMI
Line 173... Line 173... 
    .op_i(ex_alu_func_q),
 
    .op_i(ex_alu_func_q),
 
 
 
 
 
    // Operands
 
    // Operands
 
    .a_i(ex_alu_a_q),
 
    .a_i(ex_alu_a_q),
 
    .b_i(ex_alu_b_q),
 
    .b_i(ex_alu_b_q),
 
    .c_i(sr_q[`OR32_SR_CY]),
 
    .c_i(sr_q[`SR_CY]),
 
 
 
 
 
    // Result
 
    // Result
 
    .p_o(ex_result_w),
 
    .p_o(ex_result_w),
 
 
 
 
 
    // Carry
 
    // Carry
Line 188... Line 188... 
    .equal_o(compare_equal_w),
 
    .equal_o(compare_equal_w),
 
    .greater_than_signed_o(compare_gts_w),
 
    .greater_than_signed_o(compare_gts_w),
 
    .greater_than_o(compare_gt_w),
 
    .greater_than_o(compare_gt_w),
 
    .less_than_signed_o(compare_lts_w),
 
    .less_than_signed_o(compare_lts_w),
 
    .less_than_o(compare_lt_w),
 
    .less_than_o(compare_lt_w),
 
    .flag_update_o(alu_flag_update)
 
    .flag_update_o(alu_flag_update_w)
 
);
 
);
 
 
 
 
 
// Writeback result
 
// Writeback result
 
wire [31:0] w_write_res     = (state_q == STATE_MEM) ? load_result_r : ex_result_w;
 
wire [31:0] w_write_res     = (state_q == STATE_MEM) ? load_result_r : ex_result_w;
 
 
 
 
Line 696... Line 696... 
always @ *
 
always @ *
 
begin
 
begin
 
    next_sr_r = sr_q;
 
    next_sr_r = sr_q;
 
 
 
 
 
    // Update SR.F
 
    // Update SR.F
 
    if (alu_flag_update)
 
    if (alu_flag_update_w)
 
        next_sr_r[`OR32_SR_F]           = compare_result_r;
 
        next_sr_r[`SR_F]           = compare_result_r;
 
 
 
 
 
    // Latch carry if updated
 
    // Latch carry if updated
 
    if (alu_carry_update_w)
 
    if (alu_carry_update_w)
 
        next_sr_r[`OR32_SR_CY]          = alu_carry_out_w;
 
        next_sr_r[`SR_CY]          = alu_carry_out_w;
 
 
 
 
 
    case (1'b1)
 
    case (1'b1)
 
      inst_mtspr_w:
 
      inst_mtspr_w:
 
      begin
 
      begin
 
          case (mxspr_uint16_r)
 
          case (mxspr_uint16_r)
 
          // SR - Supervision register
 
          // SR - Supervision register
 
          `SPR_REG_SR:
 
          `SPR_REG_SR:
 
          begin
 
          begin
 
              next_sr_r[`OR32_SR_F]     = reg_rb_r[`OR32_SR_F];
 
              next_sr_r[`SR_F]     = reg_rb_r[`SR_F];
 
              next_sr_r[`OR32_SR_CY]    = reg_rb_r[`OR32_SR_CY];
 
              next_sr_r[`SR_CY]    = reg_rb_r[`SR_CY];
 
              next_sr_r[`OR32_SR_IEE]   = reg_rb_r[`OR32_SR_IEE];
 
              next_sr_r[`SR_IEE]   = reg_rb_r[`SR_IEE];
 
          end
 
          end
 
          default:
 
          default:
 
            ;
 
            ;
 
          endcase
 
          endcase
 
      end
 
      end
 
      inst_rfe_w:
 
      inst_rfe_w:
 
      begin
 
      begin
 
          next_sr_r[`OR32_SR_F]         = esr_q[`OR32_SR_F];
 
          next_sr_r[`SR_F]         = esr_q[`SR_F];
 
          next_sr_r[`OR32_SR_CY]        = esr_q[`OR32_SR_CY];
 
          next_sr_r[`SR_CY]        = esr_q[`SR_CY];
 
          next_sr_r[`OR32_SR_IEE]       = esr_q[`OR32_SR_IEE];
 
          next_sr_r[`SR_IEE]       = esr_q[`SR_IEE];
 
      end
 
      end
 
      inst_sfxx_w,
 
      inst_sfxx_w,
 
      inst_sfxxi_w:
 
      inst_sfxxi_w:
 
           next_sr_r[`OR32_SR_F]        = compare_result_r;
 
           next_sr_r[`SR_F]        = compare_result_r;
 
      default:
 
      default:
 
        ;
 
        ;
 
    endcase
 
    endcase
 
end
 
end
 
 
 
 
Line 893... Line 893... 
        case (mxspr_uint16_r)
 
        case (mxspr_uint16_r)
 
           // SR - Supervision register
 
           // SR - Supervision register
 
           `SPR_REG_SR:
 
           `SPR_REG_SR:
 
           begin
 
           begin
 
               alu_input_a_r                = 32'b0;
 
               alu_input_a_r                = 32'b0;
 
               alu_input_a_r[`OR32_SR_F]    = next_sr_r[`OR32_SR_F];
 
               alu_input_a_r[`SR_F]    = next_sr_r[`SR_F];
 
               alu_input_a_r[`OR32_SR_CY]   = next_sr_r[`OR32_SR_CY];
 
               alu_input_a_r[`SR_CY]   = next_sr_r[`SR_CY];
 
               alu_input_a_r[`OR32_SR_IEE]  = next_sr_r[`OR32_SR_IEE];
 
               alu_input_a_r[`SR_IEE]  = next_sr_r[`SR_IEE];
 
               write_rd_r                   = 1'b1;
 
               write_rd_r                   = 1'b1;
 
           end
 
           end
 
 
 
 
 
           // EPCR - EPC Exception saved PC
 
           // EPCR - EPC Exception saved PC
 
           `SPR_REG_EPCR:
 
           `SPR_REG_EPCR:
Line 910... Line 910... 
 
 
 
 
           // ESR - Exception saved SR
 
           // ESR - Exception saved SR
 
           `SPR_REG_ESR:
 
           `SPR_REG_ESR:
 
           begin
 
           begin
 
               alu_input_a_r                = 32'b0;
 
               alu_input_a_r                = 32'b0;
 
               alu_input_a_r[`OR32_SR_F]    = esr_q[`OR32_SR_F];
 
               alu_input_a_r[`SR_F]    = esr_q[`SR_F];
 
               alu_input_a_r[`OR32_SR_CY]   = esr_q[`OR32_SR_CY];
 
               alu_input_a_r[`SR_CY]   = esr_q[`SR_CY];
 
               alu_input_a_r[`OR32_SR_IEE]  = esr_q[`OR32_SR_IEE];
 
               alu_input_a_r[`SR_IEE]  = esr_q[`SR_IEE];
 
               write_rd_r                   = 1'b1;
 
               write_rd_r                   = 1'b1;
 
           end
 
           end
 
           default:
 
           default:
 
              ;
 
              ;
 
        endcase
 
        endcase
Line 1053... Line 1053... 
    // Default branch target is relative to current PC
 
    // Default branch target is relative to current PC
 
    branch_target_r = (pc_q + {target_int26_r[29:0],2'b00});
 
    branch_target_r = (pc_q + {target_int26_r[29:0],2'b00});
 
 
 
 
 
    case (1'b1)
 
    case (1'b1)
 
    inst_bf_w: // l.bf
 
    inst_bf_w: // l.bf
 
        branch_r      = sr_q[`OR32_SR_F];
 
        branch_r      = sr_q[`SR_F];
 
 
 
 
 
    inst_bnf_w: // l.bnf
 
    inst_bnf_w: // l.bnf
 
        branch_r      = ~sr_q[`OR32_SR_F];
 
        branch_r      = ~sr_q[`SR_F];
 
 
 
 
 
    inst_j_w: // l.j
 
    inst_j_w: // l.j
 
        branch_r      = 1'b1;
 
        branch_r      = 1'b1;
 
 
 
 
 
    inst_jal_w: // l.jal
 
    inst_jal_w: // l.jal
Line 1304... Line 1304... 
    `ifdef CONF_CORE_DEBUG
 
    `ifdef CONF_CORE_DEBUG
 
               $display(" NMI 0x%08x", ISR_VECTOR + `VECTOR_NMI);
 
               $display(" NMI 0x%08x", ISR_VECTOR + `VECTOR_NMI);
 
    `endif
 
    `endif
 
           end
 
           end
 
           // External interrupt
 
           // External interrupt
 
           else if (intr_i && next_sr_r[`OR32_SR_IEE])
 
           else if (intr_i && next_sr_r[`SR_IEE])
 
           begin
 
           begin
 
                // Save PC of next instruction & SR
 
                // Save PC of next instruction & SR
 
                if (branch_r)
 
                if (branch_r)
 
                    epc_q   <= branch_target_r;
 
                    epc_q   <= branch_target_r;
 
                // Next expected PC (current PC + 4)
 
                // Next expected PC (current PC + 4)

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