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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.1
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2014
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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input rst_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input wr_i /*verilator public*/,
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input wr_i /*verilator public*/,
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input [4:0] rs_i /*verilator public*/,
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input [4:0] rs_i /*verilator public*/,
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input [4:0] rt_i /*verilator public*/,
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input [4:0] rt_i /*verilator public*/,
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input [4:0] rd_i /*verilator public*/,
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input [4:0] rd_i /*verilator public*/,
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output [31:0] reg_rs_o /*verilator public*/,
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output reg [31:0] reg_rs_o /*verilator public*/,
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output [31:0] reg_rt_o /*verilator public*/,
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output reg [31:0] reg_rt_o /*verilator public*/,
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input [31:0] reg_rd_i /*verilator public*/
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input [31:0] reg_rd_i /*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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parameter SUPPORT_32REGS = "ENABLED";
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parameter SUPPORT_32REGS = "ENABLED";
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers
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// Registers
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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reg clk_delayed;
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wire clk_delayed;
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wire [31:0] data_out1;
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wire [31:0] data_out1;
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wire [31:0] data_out2;
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wire [31:0] data_out2;
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reg write_enable;
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reg write_enable;
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reg [31:0] reg_rs_o;
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reg [31:0] reg_rt_o;
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reg [4:0] addr_reg;
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reg [4:0] addr_reg;
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reg [31:0] data_reg;
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reg [31:0] data_reg;
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wire [31:0] q1;
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wire [31:0] q1;
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wire [31:0] q2;
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wire [31:0] q2;
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