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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2014 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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module altor32_regfile_xil
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module altor32_regfile_xil
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(
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(
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input clk_i /*verilator public*/,
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input clk_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input wr_i /*verilator public*/,
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input wr_i /*verilator public*/,
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input [4:0] rs_i /*verilator public*/,
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input [4:0] ra_i /*verilator public*/,
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input [4:0] rt_i /*verilator public*/,
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input [4:0] rb_i /*verilator public*/,
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input [4:0] rd_i /*verilator public*/,
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input [4:0] rd_i /*verilator public*/,
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output reg [31:0] reg_rs_o /*verilator public*/,
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output reg [31:0] reg_ra_o /*verilator public*/,
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output reg [31:0] reg_rt_o /*verilator public*/,
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output reg [31:0] reg_rb_o /*verilator public*/,
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input [31:0] reg_rd_i /*verilator public*/
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input [31:0] reg_rd_i /*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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parameter SUPPORT_32REGS = "ENABLED";
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parameter SUPPORT_32REGS = "ENABLED";
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers
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// Registers / Wires
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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reg [4:0] addr_write;
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wire [31:0] reg_ra_w;
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wire [31:0] data_out1;
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wire [31:0] reg_rb_w;
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wire [31:0] data_out2;
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wire [31:0] ra_0_15_w;
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reg write_enable;
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wire [31:0] ra_16_31_w;
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wire [31:0] data_out1a;
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wire [31:0] rb_0_15_w;
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wire [31:0] data_out1b;
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wire [31:0] rb_16_31_w;
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wire [31:0] data_out2a;
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wire write_enable_w;
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wire [31:0] data_out2b;
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wire write_banka_w;
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wire wea;
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wire write_bankb_w;
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wire web;
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//-----------------------------------------------------------------
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// Async Read Process
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//-----------------------------------------------------------------
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always @ (clk_i or rs_i or rt_i or rd_i or reg_rd_i or data_out1 or data_out2 or rst_i or wr_i)
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begin
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// Read Rs
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if (rs_i == 5'b00000)
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reg_rs_o <= 32'h00000000;
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else
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reg_rs_o <= data_out1;
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// Read Rt
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if (rt_i == 5'b00000)
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reg_rt_o <= 32'h00000000;
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else
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reg_rt_o <= data_out2;
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// Write enabled?
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addr_write <= rd_i[4:0];
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if ((rd_i != 5'b00000) & (wr_i == 1'b1))
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write_enable <= 1'b1;
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else
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write_enable <= 1'b0;
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end
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Register File (using RAM16X1D )
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// Register File (using RAM16X1D )
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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generate
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generate
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begin
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begin
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genvar i;
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genvar i;
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for (i=0;i<32;i=i+1)
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for (i=0;i<32;i=i+1)
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begin : reg_loop1
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begin : reg_loop1
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RAM16X1D reg_bit1a(.WCLK(clk_i), .WE(wea), .A0(addr_write[0]), .A1(addr_write[1]), .A2(addr_write[2]), .A3(addr_write[3]), .D(reg_rd_i[i]), .DPRA0(rs_i[0]), .DPRA1(rs_i[1]), .DPRA2(rs_i[2]), .DPRA3(rs_i[3]), .DPO(data_out1a[i]), .SPO(/* open */));
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RAM16X1D reg_bit1a(.WCLK(clk_i), .WE(write_banka_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(ra_i[0]), .DPRA1(ra_i[1]), .DPRA2(ra_i[2]), .DPRA3(ra_i[3]), .DPO(ra_0_15_w[i]), .SPO(/* open */));
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RAM16X1D reg_bit1b(.WCLK(clk_i), .WE(web), .A0(addr_write[0]), .A1(addr_write[1]), .A2(addr_write[2]), .A3(addr_write[3]), .D(reg_rd_i[i]), .DPRA0(rs_i[0]), .DPRA1(rs_i[1]), .DPRA2(rs_i[2]), .DPRA3(rs_i[3]), .DPO(data_out1b[i]), .SPO(/* open */));
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RAM16X1D reg_bit2a(.WCLK(clk_i), .WE(write_banka_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(rb_i[0]), .DPRA1(rb_i[1]), .DPRA2(rb_i[2]), .DPRA3(rb_i[3]), .DPO(rb_0_15_w[i]), .SPO(/* open */));
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end
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end
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end
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end
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endgenerate
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endgenerate
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// Registers 16 - 31
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// Registers 16 - 31
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if (SUPPORT_32REGS == "ENABLED")
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if (SUPPORT_32REGS == "ENABLED")
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begin
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begin
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genvar i;
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genvar i;
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for (i=0;i<32;i=i+1)
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for (i=0;i<32;i=i+1)
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begin : reg_loop2
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begin : reg_loop2
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RAM16X1D reg_bit2a(.WCLK(clk_i), .WE(wea), .A0(addr_write[0]), .A1(addr_write[1]), .A2(addr_write[2]), .A3(addr_write[3]), .D(reg_rd_i[i]), .DPRA0(rt_i[0]), .DPRA1(rt_i[1]), .DPRA2(rt_i[2]), .DPRA3(rt_i[3]), .DPO(data_out2a[i]), .SPO(/* open */));
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RAM16X1D reg_bit1b(.WCLK(clk_i), .WE(write_bankb_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(ra_i[0]), .DPRA1(ra_i[1]), .DPRA2(ra_i[2]), .DPRA3(ra_i[3]), .DPO(ra_16_31_w[i]), .SPO(/* open */));
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RAM16X1D reg_bit2b(.WCLK(clk_i), .WE(web), .A0(addr_write[0]), .A1(addr_write[1]), .A2(addr_write[2]), .A3(addr_write[3]), .D(reg_rd_i[i]), .DPRA0(rt_i[0]), .DPRA1(rt_i[1]), .DPRA2(rt_i[2]), .DPRA3(rt_i[3]), .DPO(data_out2b[i]), .SPO(/* open */));
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RAM16X1D reg_bit2b(.WCLK(clk_i), .WE(write_bankb_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(rb_i[0]), .DPRA1(rb_i[1]), .DPRA2(rb_i[2]), .DPRA3(rb_i[3]), .DPO(rb_16_31_w[i]), .SPO(/* open */));
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end
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end
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end
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end
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else
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else
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begin
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begin
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assign data_out2a = 32'h00000000;
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assign ra_16_31_w = 32'h00000000;
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assign data_out2b = 32'h00000000;
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assign rb_16_31_w = 32'h00000000;
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end
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end
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endgenerate
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endgenerate
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Combinatorial Assignments
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// Combinatorial Assignments
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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assign data_out1 = (rs_i[4] == 1'b0) ? data_out1a : data_out1b;
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assign reg_ra_w = (ra_i[4] == 1'b0) ? ra_0_15_w : ra_16_31_w;
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assign data_out2 = (rt_i[4] == 1'b0) ? data_out2a : data_out2b;
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assign reg_rb_w = (rb_i[4] == 1'b0) ? rb_0_15_w : rb_16_31_w;
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assign wea = (write_enable & ~ (addr_write[4]));
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assign web = (write_enable & addr_write[4]);
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assign write_enable_w = (rd_i != 5'b00000) & wr_i;
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assign write_banka_w = (write_enable_w & (~rd_i[4]));
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assign write_bankb_w = (write_enable_w & rd_i[4]);
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// Register read ports
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always @ *
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begin
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if (ra_i == 5'b00000)
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reg_ra_o = 32'h00000000;
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else
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reg_ra_o = reg_ra_w;
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if (rb_i == 5'b00000)
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reg_rb_o = 32'h00000000;
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else
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reg_rb_o = reg_rb_w;
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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