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[/] [altor32/] [trunk/] [rtl/] [cpu_lite/] [altor32_regfile_xil.v] - Diff between revs 36 and 37

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//               Email: admin@ultra-embedded.com
//               Email: admin@ultra-embedded.com
//
//
//                       License: LGPL
//                       License: LGPL
//-----------------------------------------------------------------
//-----------------------------------------------------------------
//
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
//
// This source file may be used and distributed without         
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
// the original copyright notice and the associated disclaimer. 
Line 46... Line 46...
module altor32_regfile_xil
module altor32_regfile_xil
(
(
    input             clk_i       /*verilator public*/,
    input             clk_i       /*verilator public*/,
    input             rst_i       /*verilator public*/,
    input             rst_i       /*verilator public*/,
    input             wr_i        /*verilator public*/,
    input             wr_i        /*verilator public*/,
    input [4:0]       rs_i        /*verilator public*/,
    input [4:0]         ra_i        /*verilator public*/,
    input [4:0]       rt_i        /*verilator public*/,
    input [4:0]         rb_i        /*verilator public*/,
    input [4:0]       rd_i        /*verilator public*/,
    input [4:0]       rd_i        /*verilator public*/,
    output reg [31:0] reg_rs_o    /*verilator public*/,
    output reg [31:0]   reg_ra_o    /*verilator public*/,
    output reg [31:0] reg_rt_o    /*verilator public*/,
    output reg [31:0]   reg_rb_o    /*verilator public*/,
    input [31:0]      reg_rd_i    /*verilator public*/
    input [31:0]      reg_rd_i    /*verilator public*/
);
);
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Params
// Params
//-----------------------------------------------------------------
//-----------------------------------------------------------------
parameter       SUPPORT_32REGS = "ENABLED";
parameter       SUPPORT_32REGS = "ENABLED";
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Registers
// Registers / Wires
//-----------------------------------------------------------------
//-----------------------------------------------------------------
reg [4:0]       addr_write;
wire [31:0]     reg_ra_w;
wire [31:0]     data_out1;
wire [31:0]     reg_rb_w;
wire [31:0]     data_out2;
wire [31:0]     ra_0_15_w;
reg             write_enable;
wire [31:0]     ra_16_31_w;
wire [31:0]     data_out1a;
wire [31:0]     rb_0_15_w;
wire [31:0]     data_out1b;
wire [31:0]     rb_16_31_w;
wire [31:0]     data_out2a;
wire            write_enable_w;
wire [31:0]     data_out2b;
wire            write_banka_w;
wire            wea;
wire            write_bankb_w;
wire            web;
 
 
 
//-----------------------------------------------------------------
 
// Async Read Process
 
//-----------------------------------------------------------------
 
always @ (clk_i or rs_i or rt_i or rd_i or reg_rd_i or data_out1 or data_out2 or rst_i or wr_i)
 
begin
 
    // Read Rs
 
    if (rs_i == 5'b00000)
 
        reg_rs_o <= 32'h00000000;
 
    else
 
        reg_rs_o <= data_out1;
 
 
 
    // Read Rt
 
    if (rt_i == 5'b00000)
 
        reg_rt_o <= 32'h00000000;
 
    else
 
        reg_rt_o <= data_out2;
 
 
 
    // Write enabled?
 
    addr_write <= rd_i[4:0];
 
    if ((rd_i != 5'b00000) & (wr_i == 1'b1))
 
        write_enable <= 1'b1;
 
    else
 
        write_enable <= 1'b0;
 
end
 
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Register File (using RAM16X1D )
// Register File (using RAM16X1D )
//-----------------------------------------------------------------
//-----------------------------------------------------------------
 
 
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generate
generate
begin
begin
   genvar i;
   genvar i;
   for (i=0;i<32;i=i+1)
   for (i=0;i<32;i=i+1)
   begin : reg_loop1
   begin : reg_loop1
       RAM16X1D reg_bit1a(.WCLK(clk_i), .WE(wea), .A0(addr_write[0]), .A1(addr_write[1]), .A2(addr_write[2]), .A3(addr_write[3]), .D(reg_rd_i[i]), .DPRA0(rs_i[0]), .DPRA1(rs_i[1]), .DPRA2(rs_i[2]), .DPRA3(rs_i[3]), .DPO(data_out1a[i]), .SPO(/* open */));
       RAM16X1D reg_bit1a(.WCLK(clk_i), .WE(write_banka_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(ra_i[0]), .DPRA1(ra_i[1]), .DPRA2(ra_i[2]), .DPRA3(ra_i[3]), .DPO(ra_0_15_w[i]), .SPO(/* open */));
       RAM16X1D reg_bit1b(.WCLK(clk_i), .WE(web), .A0(addr_write[0]), .A1(addr_write[1]), .A2(addr_write[2]), .A3(addr_write[3]), .D(reg_rd_i[i]), .DPRA0(rs_i[0]), .DPRA1(rs_i[1]), .DPRA2(rs_i[2]), .DPRA3(rs_i[3]), .DPO(data_out1b[i]), .SPO(/* open */));
       RAM16X1D reg_bit2a(.WCLK(clk_i), .WE(write_banka_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(rb_i[0]), .DPRA1(rb_i[1]), .DPRA2(rb_i[2]), .DPRA3(rb_i[3]), .DPO(rb_0_15_w[i]), .SPO(/* open */));
   end
   end
end
end
endgenerate
endgenerate
 
 
// Registers 16 - 31
// Registers 16 - 31
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if (SUPPORT_32REGS == "ENABLED")
if (SUPPORT_32REGS == "ENABLED")
begin
begin
   genvar i;
   genvar i;
   for (i=0;i<32;i=i+1)
   for (i=0;i<32;i=i+1)
   begin : reg_loop2
   begin : reg_loop2
       RAM16X1D reg_bit2a(.WCLK(clk_i), .WE(wea), .A0(addr_write[0]), .A1(addr_write[1]), .A2(addr_write[2]), .A3(addr_write[3]), .D(reg_rd_i[i]), .DPRA0(rt_i[0]), .DPRA1(rt_i[1]), .DPRA2(rt_i[2]), .DPRA3(rt_i[3]), .DPO(data_out2a[i]), .SPO(/* open */));
       RAM16X1D reg_bit1b(.WCLK(clk_i), .WE(write_bankb_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(ra_i[0]), .DPRA1(ra_i[1]), .DPRA2(ra_i[2]), .DPRA3(ra_i[3]), .DPO(ra_16_31_w[i]), .SPO(/* open */));
       RAM16X1D reg_bit2b(.WCLK(clk_i), .WE(web), .A0(addr_write[0]), .A1(addr_write[1]), .A2(addr_write[2]), .A3(addr_write[3]), .D(reg_rd_i[i]), .DPRA0(rt_i[0]), .DPRA1(rt_i[1]), .DPRA2(rt_i[2]), .DPRA3(rt_i[3]), .DPO(data_out2b[i]), .SPO(/* open */));
       RAM16X1D reg_bit2b(.WCLK(clk_i), .WE(write_bankb_w), .A0(rd_i[0]), .A1(rd_i[1]), .A2(rd_i[2]), .A3(rd_i[3]), .D(reg_rd_i[i]), .DPRA0(rb_i[0]), .DPRA1(rb_i[1]), .DPRA2(rb_i[2]), .DPRA3(rb_i[3]), .DPO(rb_16_31_w[i]), .SPO(/* open */));
   end
   end
end
end
else
else
begin
begin
    assign data_out2a = 32'h00000000;
    assign ra_16_31_w = 32'h00000000;
    assign data_out2b = 32'h00000000;
    assign rb_16_31_w = 32'h00000000;
end
end
endgenerate
endgenerate
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Combinatorial Assignments
// Combinatorial Assignments
//-----------------------------------------------------------------
//-----------------------------------------------------------------
assign data_out1  = (rs_i[4] == 1'b0) ? data_out1a : data_out1b;
assign reg_ra_w       = (ra_i[4] == 1'b0) ? ra_0_15_w : ra_16_31_w;
assign data_out2  = (rt_i[4] == 1'b0) ? data_out2a : data_out2b;
assign reg_rb_w       = (rb_i[4] == 1'b0) ? rb_0_15_w : rb_16_31_w;
assign wea        = (write_enable & ~ (addr_write[4]));
 
assign web        = (write_enable & addr_write[4]);
assign write_enable_w = (rd_i != 5'b00000) & wr_i;
 
 
 
assign write_banka_w  = (write_enable_w & (~rd_i[4]));
 
assign write_bankb_w  = (write_enable_w & rd_i[4]);
 
 
 
// Register read ports
 
always @ *
 
begin
 
    if (ra_i == 5'b00000)
 
        reg_ra_o = 32'h00000000;
 
    else
 
        reg_ra_o = reg_ra_w;
 
 
 
    if (rb_i == 5'b00000)
 
        reg_rb_o = 32'h00000000;
 
    else
 
        reg_rb_o = reg_rb_w;
 
end
 
 
endmodule
endmodule
 
 
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