| Line 63... |
Line 63... |
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// Peripheral bus
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// Peripheral bus
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addr_i,
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addr_i,
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data_o,
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data_o,
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data_i,
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data_i,
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wr_i,
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we_i,
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rd_i
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stb_i
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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| Line 92... |
Line 92... |
input intr7_i /*verilator public*/;
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input intr7_i /*verilator public*/;
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input [(EXTERNAL_INTERRUPTS - 1):0] intr_ext_i /*verilator public*/;
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input [(EXTERNAL_INTERRUPTS - 1):0] intr_ext_i /*verilator public*/;
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input [7:0] addr_i /*verilator public*/;
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input [7:0] addr_i /*verilator public*/;
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output [31:0] data_o /*verilator public*/;
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output [31:0] data_o /*verilator public*/;
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input [31:0] data_i /*verilator public*/;
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input [31:0] data_i /*verilator public*/;
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input [3:0] wr_i /*verilator public*/;
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input we_i /*verilator public*/;
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input rd_i /*verilator public*/;
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input stb_i /*verilator public*/;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers / Wires
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// Registers / Wires
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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reg [31:0] data_o;
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reg [31:0] data_o;
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| Line 173... |
Line 173... |
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// Generate interrupt based on masked status
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// Generate interrupt based on masked status
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intr_o <= ((v_irq_status & irq_mask) != {(INTERRUPT_COUNT){1'b0}}) ? 1'b1 : 1'b0;
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intr_o <= ((v_irq_status & irq_mask) != {(INTERRUPT_COUNT){1'b0}}) ? 1'b1 : 1'b0;
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// Write Cycle
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// Write Cycle
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if (wr_i != 4'b0000)
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if (we_i & stb_i)
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begin
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begin
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case (addr_i)
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case (addr_i)
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|
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`IRQ_MASK_SET :
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`IRQ_MASK_SET :
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irq_mask <= (irq_mask | data_i[INTERRUPT_COUNT-1:0]);
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irq_mask <= (irq_mask | data_i[INTERRUPT_COUNT-1:0]);
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| Line 196... |
Line 196... |
end
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end
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Peripheral Register Read
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// Peripheral Register Read
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ (posedge rst_i or posedge clk_i )
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always @ *
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begin
|
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if (rst_i == 1'b1)
|
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begin
|
|
data_o <= 32'h00000000;
|
|
end
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else
|
|
begin
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// Read cycle?
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|
if (rd_i == 1'b1)
|
|
begin
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begin
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case (addr_i[7:0])
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case (addr_i[7:0])
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|
|
`IRQ_MASK_SET :
|
`IRQ_MASK_SET :
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data_o <= {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
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data_o = {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
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|
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`IRQ_MASK_CLR :
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`IRQ_MASK_CLR :
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data_o <= {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
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data_o = {{(32-INTERRUPT_COUNT){1'b0}}, irq_mask};
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|
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`IRQ_STATUS :
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`IRQ_STATUS :
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data_o <= {{(32-INTERRUPT_COUNT){1'b0}}, irq_status};
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data_o = {{(32-INTERRUPT_COUNT){1'b0}}, irq_status};
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|
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default :
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default :
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data_o <= 32'h00000000;
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data_o = 32'h00000000;
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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