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[/] [altor32/] [trunk/] [rtl/] [peripheral/] [timer_periph.v] - Diff between revs 27 and 32

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Rev 27 Rev 32
Line 55... Line 55...
 
 
    // Peripheral bus
    // Peripheral bus
    addr_i,
    addr_i,
    data_o,
    data_o,
    data_i,
    data_i,
    wr_i,
    we_i,
    rd_i
    stb_i
);
);
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Params
// Params
//-----------------------------------------------------------------
//-----------------------------------------------------------------
Line 79... Line 79...
output              intr_hires_o /*verilator public*/;
output              intr_hires_o /*verilator public*/;
 
 
input [7:0]         addr_i /*verilator public*/;
input [7:0]         addr_i /*verilator public*/;
output [31:0]       data_o /*verilator public*/;
output [31:0]       data_o /*verilator public*/;
input [31:0]        data_i /*verilator public*/;
input [31:0]        data_i /*verilator public*/;
input [3:0]         wr_i /*verilator public*/;
input               we_i /*verilator public*/;
input               rd_i /*verilator public*/;
input               stb_i /*verilator public*/;
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Registers / Wires
// Registers / Wires
//-----------------------------------------------------------------
//-----------------------------------------------------------------
 
 
Line 229... Line 229...
       hr_timer_match   <= 32'h00000000;
       hr_timer_match   <= 32'h00000000;
   end
   end
   else
   else
   begin
   begin
       // Write Cycle
       // Write Cycle
       if (wr_i != 4'b0000)
       if (we_i & stb_i)
       begin
       begin
           case (addr_i)
           case (addr_i)
 
 
           `TIMER_HIRES :
           `TIMER_HIRES :
                hr_timer_match <= data_i;
                hr_timer_match <= data_i;
Line 246... Line 246...
end
end
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Peripheral Register Read
// Peripheral Register Read
//-----------------------------------------------------------------
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
always @ *
begin
 
   if (rst_i == 1'b1)
 
   begin
 
       data_o       <= 32'h00000000;
 
   end
 
   else
 
   begin
 
       // Read cycle?
 
       if (rd_i == 1'b1)
 
       begin
       begin
           case (addr_i[7:0])
           case (addr_i[7:0])
 
 
           // 32-bit systick/1ms counter
           // 32-bit systick/1ms counter
           `TIMER_SYSTICK_VAL :
           `TIMER_SYSTICK_VAL :
                data_o <= systick_count;
        data_o = systick_count;
 
 
           // Hi res timer (clock rate)
           // Hi res timer (clock rate)
           `TIMER_HIRES :
           `TIMER_HIRES :
                data_o <= hr_timer_cnt;
        data_o = hr_timer_cnt;
 
 
           default :
           default :
                data_o <= 32'h00000000;
        data_o = 32'h00000000;
           endcase
           endcase
        end
        end
   end
 
end
 
 
 
endmodule
endmodule
 
 
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