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[/] [altor32/] [trunk/] [rtl/] [soc/] [cpu_if.v] - Diff between revs 27 and 32

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//-----------------------------------------------------------------
 
 
 
//                           AltOR32 
 
 
//                Alternative Lightweight OpenRisc 
 
 
//                            V2.0
 
 
 
//                     Ultra-Embedded.com
 
 
 
//                   Copyright 2011 - 2013
 
 
 
//
 
 
 
//               Email: admin@ultra-embedded.com
 
 
 
//
 
 
 
//                       License: LGPL
 
 
 
//-----------------------------------------------------------------
 
 
 
//
 
 
 
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
 
 
 
//
 
 
 
// This source file may be used and distributed without         
 
 
// restriction provided that this copyright statement is not    
 
 
// removed from the file and that any derivative work contains  
 
 
// the original copyright notice and the associated disclaimer. 
 
 
//
 
 
 
// This source file is free software; you can redistribute it   
 
 
// and/or modify it under the terms of the GNU Lesser General   
 
 
// Public License as published by the Free Software Foundation; 
 
 
// either version 2.1 of the License, or (at your option) any   
 
 
// later version.
 
 
 
//
 
 
 
// This source is distributed in the hope that it will be       
 
 
// useful, but WITHOUT ANY WARRANTY; without even the implied   
 
 
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
 
 
// PURPOSE.  See the GNU Lesser General Public License for more 
 
 
// details.
 
 
 
//
 
 
 
// You should have received a copy of the GNU Lesser General    
 
 
// Public License along with this source; if not, write to the 
 
 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
 
 
// Boston, MA  02111-1307  USA
 
 
 
//-----------------------------------------------------------------
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// Module:
 
// Module:
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
module cpu_if
 
module cpu_if
 
(
 
(
 
    // General - Clocking & Reset
 
    // General - Clocking & Reset
 
    clk_i,
 
    input               clk_i,
 
    rst_i,
 
    input               rst_i,
 
 
 
 
 
    // Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
 
    // Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
 
    imem0_addr_o,
 
    output [31:0]       imem0_addr_o,
 
    imem0_rd_o,
 
    input [31:0]        imem0_data_i,
 
    imem0_burst_o,
 
    output [3:0]        imem0_sel_o,
 
    imem0_data_in_i,
 
    output              imem0_stb_o,
 
    imem0_accept_i,
 
    output              imem0_cyc_o,
 
    imem0_ack_i,
 
    output [2:0]        imem0_cti_o,
 
 
 
    input               imem0_ack_i,
 
 
 
    input               imem0_stall_i,
 
 
 
 
 
    // Data Memory 0 (0x10000000 - 0x10FFFFFF)
 
    // Data Memory 0 (0x10000000 - 0x10FFFFFF)
 
    dmem0_addr_o,
 
    output [31:0]       dmem0_addr_o,
 
    dmem0_data_o,
 
    output [31:0]       dmem0_data_o,
 
    dmem0_data_i,
 
    input [31:0]        dmem0_data_i,
 
    dmem0_wr_o,
 
    output [3:0]        dmem0_sel_o,
 
    dmem0_rd_o,
 
    output              dmem0_we_o,
 
    dmem0_burst_o,
 
    output              dmem0_stb_o,
 
    dmem0_accept_i,
 
    output              dmem0_cyc_o,
 
    dmem0_ack_i,
 
    output [2:0]        dmem0_cti_o,
 
 
 
    input               dmem0_ack_i,
 
 
 
    input               dmem0_stall_i,
 
 
 
 
 
    // Data Memory 1 (0x11000000 - 0x11FFFFFF)
 
    // Data Memory 1 (0x11000000 - 0x11FFFFFF)
 
    dmem1_addr_o,
 
    output [31:0]       dmem1_addr_o,
 
    dmem1_data_o,
 
    output [31:0]       dmem1_data_o,
 
    dmem1_data_i,
 
    input [31:0]        dmem1_data_i,
 
    dmem1_wr_o,
 
    output [3:0]        dmem1_sel_o,
 
    dmem1_rd_o,
 
    output              dmem1_we_o,
 
    dmem1_burst_o,
 
    output              dmem1_stb_o,
 
    dmem1_accept_i,
 
    output              dmem1_cyc_o,
 
    dmem1_ack_i,
 
    output [2:0]        dmem1_cti_o,
 
 
 
    input               dmem1_ack_i,
 
 
 
    input               dmem1_stall_i,
 
 
 
 
 
    // Data Memory 2 (0x12000000 - 0x12FFFFFF)
 
    // Data Memory 2 (0x12000000 - 0x12FFFFFF)
 
    dmem2_addr_o,
 
    output [31:0]       dmem2_addr_o,
 
    dmem2_data_o,
 
    output [31:0]       dmem2_data_o,
 
    dmem2_data_i,
 
    input [31:0]        dmem2_data_i,
 
    dmem2_wr_o,
 
    output [3:0]        dmem2_sel_o,
 
    dmem2_rd_o,
 
    output              dmem2_we_o,
 
    dmem2_burst_o,
 
    output              dmem2_stb_o,
 
    dmem2_accept_i,
 
    output              dmem2_cyc_o,
 
    dmem2_ack_i,
 
    output [2:0]        dmem2_cti_o,
 
 
 
    input               dmem2_ack_i,
 
    fault_o,
 
    input               dmem2_stall_i,
 
    break_o,
 
 
 
    intr_i,
 
    output              fault_o,
 
    nmi_i
 
    output              break_o,
 
 
 
    input               intr_i,
 
 
 
    input               nmi_i
 
);
 
);
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// Params
 
// Params
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
parameter  [31:0]   CLK_KHZ              = 12288;
 
parameter           CLK_KHZ              = 12288;
 
parameter           ENABLE_ICACHE        = "ENABLED";
 
parameter           ENABLE_ICACHE        = "ENABLED";
 
parameter           ENABLE_DCACHE        = "DISABLED";
 
parameter           ENABLE_DCACHE        = "ENABLED";
 
parameter           BOOT_VECTOR          = 0;
 
parameter           BOOT_VECTOR          = 0;
 
parameter           ISR_VECTOR           = 0;
 
parameter           ISR_VECTOR           = 0;
 
parameter           REGISTER_FILE_TYPE   = "SIMULATION";
 
parameter           REGISTER_FILE_TYPE   = "SIMULATION";
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// I/O
 
 
 
//-----------------------------------------------------------------
 
 
 
input               clk_i /*verilator public*/;
 
 
 
input               rst_i /*verilator public*/;
 
 
 
 
 
 
 
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
 
 
 
output [31:0]       imem0_addr_o /*verilator public*/;
 
 
 
output              imem0_rd_o /*verilator public*/;
 
 
 
output              imem0_burst_o /*verilator public*/;
 
 
 
input [31:0]        imem0_data_in_i /*verilator public*/;
 
 
 
input               imem0_accept_i /*verilator public*/;
 
 
 
input               imem0_ack_i /*verilator public*/;
 
 
 
 
 
 
 
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
 
 
 
output [31:0]       dmem0_addr_o /*verilator public*/;
 
 
 
output [31:0]       dmem0_data_o /*verilator public*/;
 
 
 
input [31:0]        dmem0_data_i /*verilator public*/;
 
 
 
output [3:0]        dmem0_wr_o /*verilator public*/;
 
 
 
output              dmem0_rd_o /*verilator public*/;
 
 
 
output              dmem0_burst_o /*verilator public*/;
 
 
 
input               dmem0_accept_i /*verilator public*/;
 
 
 
input               dmem0_ack_i /*verilator public*/;
 
 
 
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
 
 
 
output [31:0]       dmem1_addr_o /*verilator public*/;
 
 
 
output [31:0]       dmem1_data_o /*verilator public*/;
 
 
 
input [31:0]        dmem1_data_i /*verilator public*/;
 
 
 
output [3:0]        dmem1_wr_o /*verilator public*/;
 
 
 
output              dmem1_rd_o /*verilator public*/;
 
 
 
output              dmem1_burst_o /*verilator public*/;
 
 
 
input               dmem1_accept_i /*verilator public*/;
 
 
 
input               dmem1_ack_i /*verilator public*/;
 
 
 
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
 
 
 
output [31:0]       dmem2_addr_o /*verilator public*/;
 
 
 
output [31:0]       dmem2_data_o /*verilator public*/;
 
 
 
input [31:0]        dmem2_data_i /*verilator public*/;
 
 
 
output [3:0]        dmem2_wr_o /*verilator public*/;
 
 
 
output              dmem2_rd_o /*verilator public*/;
 
 
 
output              dmem2_burst_o /*verilator public*/;
 
 
 
input               dmem2_accept_i /*verilator public*/;
 
 
 
input               dmem2_ack_i /*verilator public*/;
 
 
 
 
 
 
 
output              fault_o /*verilator public*/;
 
 
 
output              break_o /*verilator public*/;
 
 
 
input               nmi_i /*verilator public*/;
 
 
 
input               intr_i /*verilator public*/;
 
 
 
 
 
 
 
//-----------------------------------------------------------------
 
 
 
// Registers
 
// Registers
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
wire [31:0]         cpu_address;
 
wire [31:0]         dmem_addr;
 
wire [3:0]          cpu_wr;
 
wire [31:0]         dmem_data_w;
 
wire                cpu_rd;
 
wire [31:0]         dmem_data_r;
 
wire                cpu_burst;
 
wire [3:0]          dmem_sel;
 
wire [31:0]         cpu_data_w;
 
wire [2:0]          dmem_cti;
 
wire [31:0]         cpu_data_r;
 
wire                dmem_cyc;
 
wire                cpu_accept;
 
wire                dmem_we;
 
wire                cpu_ack;
 
wire                dmem_stb;
 
 
 
wire                dmem_stall;
 
 
 
wire                dmem_ack;
 
 
 
 
 
wire [31:0]         imem_address;
 
wire [31:0]         imem_address;
 
wire [31:0]         imem_data;
 
wire [31:0]         imem_data;
 
wire                imem_rd;
 
wire [2:0]          imem_cti;
 
wire                imem_burst;
 
wire                imem_cyc;
 
 
 
wire                imem_stb;
 
 
 
wire                imem_stall;
 
wire                imem_ack;
 
wire                imem_ack;
 
wire                imem_accept;
 
 
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// CPU core
 
// CPU core
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
cpu
 
cpu
Line 149... Line 151... 
    .fault_o(fault_o),
 
    .fault_o(fault_o),
 
    .break_o(break_o),
 
    .break_o(break_o),
 
 
 
 
 
    // Instruction memory
 
    // Instruction memory
 
    .imem_addr_o(imem_address),
 
    .imem_addr_o(imem_address),
 
    .imem_rd_o(imem_rd),
 
    .imem_dat_i(imem_data),
 
    .imem_burst_o(imem_burst),
 
    .imem_cti_o(imem_cti),
 
    .imem_data_in_i(imem_data),
 
    .imem_cyc_o(imem_cyc),
 
    .imem_accept_i(imem_accept),
 
    .imem_stb_o(imem_stb),
 
 
 
    .imem_stall_i(imem_stall),
 
    .imem_ack_i(imem_ack),
 
    .imem_ack_i(imem_ack),
 
 
 
 
 
    // Data memory
 
    // Data memory
 
    .dmem_addr_o(cpu_address),
 
    .dmem_addr_o(dmem_addr),
 
    .dmem_data_out_o(cpu_data_w),
 
    .dmem_dat_o(dmem_data_w),
 
    .dmem_data_in_i(cpu_data_r),
 
    .dmem_dat_i(dmem_data_r),
 
    .dmem_wr_o(cpu_wr),
 
    .dmem_sel_o(dmem_sel),
 
    .dmem_rd_o(cpu_rd),
 
    .dmem_cti_o(dmem_cti),
 
    .dmem_burst_o(cpu_burst),
 
    .dmem_cyc_o(dmem_cyc),
 
    .dmem_accept_i(cpu_accept),
 
    .dmem_we_o(dmem_we),
 
    .dmem_ack_i(cpu_ack)
 
    .dmem_stb_o(dmem_stb),
 
 
 
    .dmem_stall_i(dmem_stall),
 
 
 
    .dmem_ack_i(dmem_ack)
 
);
 
);
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// Instruction Memory MUX
 
// Instruction Memory MUX
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
 
 
 
 
assign imem0_addr_o     = imem_address;
 
assign imem0_addr_o     = imem_address;
 
assign imem0_rd_o       = imem_rd;
 
assign imem0_sel_o      = 4'b1111;
 
assign imem0_burst_o    = imem_burst;
 
assign imem0_stb_o      = imem_stb;
 
assign imem_data        = imem0_data_in_i;
 
assign imem0_cyc_o      = imem_cyc;
 
assign imem_accept      = imem0_accept_i;
 
assign imem0_cti_o      = imem_cti;
 
 
 
assign imem_data        = imem0_data_i;
 
 
 
assign imem_stall       = imem0_stall_i;
 
assign imem_ack         = imem0_ack_i;
 
assign imem_ack         = imem0_ack_i;
 
 
 
 
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// Data Memory MUX
 
// Data Memory MUX
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    // Outputs
 
    // Outputs
 
    // 0x10000000 - 0x10FFFFFF
 
    // 0x10000000 - 0x10FFFFFF
 
    .out0_addr_o(dmem0_addr_o),
 
    .out0_addr_o(dmem0_addr_o),
 
    .out0_data_o(dmem0_data_o),
 
    .out0_data_o(dmem0_data_o),
 
    .out0_data_i(dmem0_data_i),
 
    .out0_data_i(dmem0_data_i),
 
    .out0_wr_o(dmem0_wr_o),
 
    .out0_sel_o(dmem0_sel_o),
 
    .out0_rd_o(dmem0_rd_o),
 
    .out0_we_o(dmem0_we_o),
 
    .out0_burst_o(dmem0_burst_o),
 
    .out0_stb_o(dmem0_stb_o),
 
 
 
    .out0_cyc_o(dmem0_cyc_o),
 
 
 
    .out0_cti_o(dmem0_cti_o),
 
    .out0_ack_i(dmem0_ack_i),
 
    .out0_ack_i(dmem0_ack_i),
 
    .out0_accept_i(dmem0_accept_i),
 
    .out0_stall_i(dmem0_stall_i),
 
 
 
 
 
    // 0x11000000 - 0x11FFFFFF
 
    // 0x11000000 - 0x11FFFFFF
 
    .out1_addr_o(dmem1_addr_o),
 
    .out1_addr_o(dmem1_addr_o),
 
    .out1_data_o(dmem1_data_o),
 
    .out1_data_o(dmem1_data_o),
 
    .out1_data_i(dmem1_data_i),
 
    .out1_data_i(dmem1_data_i),
 
    .out1_wr_o(dmem1_wr_o),
 
    .out1_sel_o(dmem1_sel_o),
 
    .out1_rd_o(dmem1_rd_o),
 
    .out1_we_o(dmem1_we_o),
 
    .out1_burst_o(dmem1_burst_o),
 
    .out1_stb_o(dmem1_stb_o),
 
 
 
    .out1_cyc_o(dmem1_cyc_o),
 
 
 
    .out1_cti_o(dmem1_cti_o),
 
    .out1_ack_i(dmem1_ack_i),
 
    .out1_ack_i(dmem1_ack_i),
 
    .out1_accept_i(dmem1_accept_i),
 
    .out1_stall_i(dmem1_stall_i),
 
 
 
 
 
    // 0x12000000 - 0x12FFFFFF
 
    // 0x12000000 - 0x12FFFFFF
 
    .out2_addr_o(dmem2_addr_o),
 
    .out2_addr_o(dmem2_addr_o),
 
    .out2_data_o(dmem2_data_o),
 
    .out2_data_o(dmem2_data_o),
 
    .out2_data_i(dmem2_data_i),
 
    .out2_data_i(dmem2_data_i),
 
    .out2_wr_o(dmem2_wr_o),
 
    .out2_sel_o(dmem2_sel_o),
 
    .out2_rd_o(dmem2_rd_o),
 
    .out2_we_o(dmem2_we_o),
 
    .out2_burst_o(dmem2_burst_o),
 
    .out2_stb_o(dmem2_stb_o),
 
 
 
    .out2_cyc_o(dmem2_cyc_o),
 
 
 
    .out2_cti_o(dmem2_cti_o),
 
    .out2_ack_i(dmem2_ack_i),
 
    .out2_ack_i(dmem2_ack_i),
 
    .out2_accept_i(dmem2_accept_i),
 
    .out2_stall_i(dmem2_stall_i),
 
 
 
 
 
    // Input - CPU core bus
 
    // Input - CPU core bus
 
    .mem_addr_i(cpu_address),
 
    .mem_addr_i(dmem_addr),
 
    .mem_data_i(cpu_data_w),
 
    .mem_data_i(dmem_data_w),
 
    .mem_data_o(cpu_data_r),
 
    .mem_data_o(dmem_data_r),
 
    .mem_wr_i(cpu_wr),
 
    .mem_sel_i(dmem_sel),
 
    .mem_rd_i(cpu_rd),
 
    .mem_we_i(dmem_we),
 
    .mem_burst_i(cpu_burst),
 
    .mem_stb_i(dmem_stb),
 
    .mem_ack_o(cpu_ack),
 
    .mem_cyc_i(dmem_cyc),
 
    .mem_accept_o(cpu_accept)
 
    .mem_cti_i(dmem_cti),
 
 
 
    .mem_ack_o(dmem_ack),
 
 
 
    .mem_stall_o(dmem_stall)
 
);
 
);
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
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