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//-----------------------------------------------------------------
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// AltOR32
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// Alternative Lightweight OpenRisc
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// V2.0
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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//
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// Email: admin@ultra-embedded.com
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//
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// License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module:
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// Module:
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module dmem_mux3
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module dmem_mux3
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(
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(
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// Outputs
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// Outputs
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out0_addr_o,
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output reg [31:0] out0_addr_o,
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out0_data_o,
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output reg [31:0] out0_data_o,
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out0_data_i,
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input [31:0] out0_data_i,
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out0_wr_o,
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output reg [3:0] out0_sel_o,
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out0_rd_o,
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output reg out0_we_o,
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out0_burst_o,
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output reg out0_stb_o,
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out0_ack_i,
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output reg out0_cyc_o,
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out0_accept_i,
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output reg [2:0] out0_cti_o,
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out1_addr_o,
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input out0_ack_i,
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out1_data_o,
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input out0_stall_i,
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out1_data_i,
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out1_wr_o,
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output reg [31:0] out1_addr_o,
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out1_rd_o,
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output reg [31:0] out1_data_o,
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out1_burst_o,
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input [31:0] out1_data_i,
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out1_ack_i,
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output reg [3:0] out1_sel_o,
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out1_accept_i,
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output reg out1_we_o,
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out2_addr_o,
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output reg out1_stb_o,
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out2_data_o,
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output reg out1_cyc_o,
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out2_data_i,
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output reg [2:0] out1_cti_o,
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out2_wr_o,
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input out1_ack_i,
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out2_rd_o,
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input out1_stall_i,
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out2_burst_o,
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out2_ack_i,
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output reg [31:0] out2_addr_o,
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out2_accept_i,
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output reg [31:0] out2_data_o,
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input [31:0] out2_data_i,
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output reg [3:0] out2_sel_o,
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output reg out2_we_o,
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output reg out2_stb_o,
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output reg out2_cyc_o,
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output reg [2:0] out2_cti_o,
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input out2_ack_i,
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input out2_stall_i,
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// Input
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// Input
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mem_addr_i,
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input [31:0] mem_addr_i,
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mem_data_i,
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input [31:0] mem_data_i,
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mem_data_o,
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output reg[31:0] mem_data_o,
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mem_burst_i,
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input [3:0] mem_sel_i,
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mem_wr_i,
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input mem_we_i,
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mem_rd_i,
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input mem_stb_i,
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mem_ack_o,
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input mem_cyc_i,
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mem_accept_o
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input [2:0] mem_cti_i,
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output reg mem_ack_o,
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output reg mem_stall_o
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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parameter ADDR_MUX_START = 28;
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parameter ADDR_MUX_START = 28;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// I/O
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// Request
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//-----------------------------------------------------------------
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input [31:0] mem_addr_i /*verilator public*/;
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input [31:0] mem_data_i /*verilator public*/;
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output [31:0] mem_data_o /*verilator public*/;
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input [3:0] mem_wr_i /*verilator public*/;
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input mem_rd_i /*verilator public*/;
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input mem_burst_i /*verilator public*/;
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output mem_ack_o /*verilator public*/;
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output mem_accept_o /*verilator public*/;
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output [31:0] out0_addr_o /*verilator public*/;
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output [31:0] out0_data_o /*verilator public*/;
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input [31:0] out0_data_i /*verilator public*/;
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output [3:0] out0_wr_o /*verilator public*/;
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output out0_rd_o /*verilator public*/;
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output out0_burst_o /*verilator public*/;
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input out0_ack_i /*verilator public*/;
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input out0_accept_i /*verilator public*/;
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output [31:0] out1_addr_o /*verilator public*/;
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output [31:0] out1_data_o /*verilator public*/;
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input [31:0] out1_data_i /*verilator public*/;
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output [3:0] out1_wr_o /*verilator public*/;
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output out1_rd_o /*verilator public*/;
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output out1_burst_o /*verilator public*/;
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input out1_ack_i /*verilator public*/;
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input out1_accept_i /*verilator public*/;
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output [31:0] out2_addr_o /*verilator public*/;
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output [31:0] out2_data_o /*verilator public*/;
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input [31:0] out2_data_i /*verilator public*/;
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output [3:0] out2_wr_o /*verilator public*/;
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output out2_rd_o /*verilator public*/;
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output out2_burst_o /*verilator public*/;
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input out2_ack_i /*verilator public*/;
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input out2_accept_i /*verilator public*/;
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//-----------------------------------------------------------------
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// Registers
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//-----------------------------------------------------------------
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// Output Signals
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reg mem_ack_o;
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reg mem_accept_o;
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reg [31:0] mem_data_o;
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reg [31:0] out0_addr_o;
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reg [31:0] out0_data_o;
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reg [3:0] out0_wr_o;
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reg out0_rd_o;
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reg out0_burst_o;
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reg [31:0] out1_addr_o;
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reg [31:0] out1_data_o;
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reg [3:0] out1_wr_o;
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reg out1_rd_o;
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reg out1_burst_o;
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reg [31:0] out2_addr_o;
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reg [31:0] out2_data_o;
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reg [3:0] out2_wr_o;
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reg out2_rd_o;
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reg out2_burst_o;
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//-----------------------------------------------------------------
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// Memory Map
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ (mem_addr_i or mem_wr_i or mem_rd_i or mem_data_i or mem_burst_i)
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always @ *
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begin
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begin
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out0_addr_o = 32'h00000000;
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out0_addr_o = 32'h00000000;
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out0_wr_o = 4'b0000;
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out0_rd_o = 1'b0;
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out0_data_o = 32'h00000000;
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out0_data_o = 32'h00000000;
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out0_burst_o = 1'b0;
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out0_sel_o = 4'b0000;
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out0_we_o = 1'b0;
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out0_stb_o = 1'b0;
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out0_cyc_o = 1'b0;
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out0_cti_o = 3'b0;
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out1_addr_o = 32'h00000000;
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out1_addr_o = 32'h00000000;
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out1_wr_o = 4'b0000;
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out1_rd_o = 1'b0;
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out1_data_o = 32'h00000000;
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out1_data_o = 32'h00000000;
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out1_burst_o = 1'b0;
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out1_sel_o = 4'b0000;
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out1_we_o = 1'b0;
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out1_stb_o = 1'b0;
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out1_cyc_o = 1'b0;
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out1_cti_o = 3'b0;
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out2_addr_o = 32'h00000000;
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out2_addr_o = 32'h00000000;
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out2_wr_o = 4'b0000;
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out2_rd_o = 1'b0;
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out2_data_o = 32'h00000000;
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out2_data_o = 32'h00000000;
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out2_burst_o = 1'b0;
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out2_sel_o = 4'b0000;
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out2_we_o = 1'b0;
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out2_stb_o = 1'b0;
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out2_cyc_o = 1'b0;
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out2_cti_o = 3'b0;
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case (mem_addr_i[ADDR_MUX_START+2-1:ADDR_MUX_START])
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case (mem_addr_i[ADDR_MUX_START+2-1:ADDR_MUX_START])
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2'd0:
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2'd0:
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begin
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begin
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out0_addr_o = mem_addr_i;
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out0_addr_o = mem_addr_i;
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out0_wr_o = mem_wr_i;
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out0_rd_o = mem_rd_i;
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out0_data_o = mem_data_i;
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out0_data_o = mem_data_i;
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out0_burst_o = mem_burst_i;
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out0_sel_o = mem_sel_i;
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out0_we_o = mem_we_i;
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out0_stb_o = mem_stb_i;
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out0_cyc_o = mem_cyc_i;
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out0_cti_o = mem_cti_i;
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end
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end
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2'd1:
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2'd1:
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begin
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begin
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out1_addr_o = mem_addr_i;
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out1_addr_o = mem_addr_i;
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out1_wr_o = mem_wr_i;
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out1_rd_o = mem_rd_i;
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out1_data_o = mem_data_i;
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out1_data_o = mem_data_i;
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out1_burst_o = mem_burst_i;
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out1_sel_o = mem_sel_i;
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out1_we_o = mem_we_i;
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out1_stb_o = mem_stb_i;
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out1_cyc_o = mem_cyc_i;
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out1_cti_o = mem_cti_i;
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end
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end
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2'd2:
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2'd2:
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begin
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begin
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out2_addr_o = mem_addr_i;
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out2_addr_o = mem_addr_i;
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out2_wr_o = mem_wr_i;
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out2_rd_o = mem_rd_i;
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out2_data_o = mem_data_i;
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out2_data_o = mem_data_i;
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out2_burst_o = mem_burst_i;
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out2_sel_o = mem_sel_i;
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out2_we_o = mem_we_i;
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out2_stb_o = mem_stb_i;
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out2_cyc_o = mem_cyc_i;
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out2_cti_o = mem_cti_i;
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end
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end
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default :
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default :
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;
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;
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endcase
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endcase
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end
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end
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Read Port
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// Response
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ *
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always @ *
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begin
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begin
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case (mem_addr_i[ADDR_MUX_START+2-1:ADDR_MUX_START])
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case (mem_addr_i[ADDR_MUX_START+2-1:ADDR_MUX_START])
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2'd0:
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2'd0:
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begin
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begin
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mem_data_o = out0_data_i;
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mem_data_o = out0_data_i;
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mem_accept_o = out0_accept_i;
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mem_stall_o = out0_stall_i;
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mem_ack_o = out0_ack_i;
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mem_ack_o = out0_ack_i;
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end
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end
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2'd1:
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2'd1:
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begin
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begin
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mem_data_o = out1_data_i;
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mem_data_o = out1_data_i;
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mem_accept_o = out1_accept_i;
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mem_stall_o = out1_stall_i;
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mem_ack_o = out1_ack_i;
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mem_ack_o = out1_ack_i;
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end
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end
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2'd2:
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2'd2:
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begin
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begin
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mem_data_o = out2_data_i;
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mem_data_o = out2_data_i;
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mem_accept_o = out2_accept_i;
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mem_stall_o = out2_stall_i;
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mem_ack_o = out2_ack_i;
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mem_ack_o = out2_ack_i;
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end
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end
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default :
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default :
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begin
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begin
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mem_data_o = 32'h00000000;
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mem_data_o = 32'h00000000;
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mem_accept_o = 1'b0;
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mem_stall_o = 1'b0;
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mem_ack_o = 1'b0;
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mem_ack_o = 1'b0;
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end
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end
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endcase
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endcase
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end
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end
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