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[/] [altor32/] [trunk/] [rtl/] [soc/] [soc.v] - Diff between revs 27 and 32

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Line 1... Line 1... 
 
 
//-----------------------------------------------------------------
 
 
 
//                           AltOR32 
 
 
//                Alternative Lightweight OpenRisc 
 
 
//                            V2.0
 
 
 
//                     Ultra-Embedded.com
 
 
 
//                   Copyright 2011 - 2013
 
 
 
//
 
 
 
//               Email: admin@ultra-embedded.com
 
 
 
//
 
 
 
//                       License: LGPL
 
 
 
//-----------------------------------------------------------------
 
 
 
//
 
 
 
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
 
 
 
//
 
 
 
// This source file may be used and distributed without         
 
 
// restriction provided that this copyright statement is not    
 
 
// removed from the file and that any derivative work contains  
 
 
// the original copyright notice and the associated disclaimer. 
 
 
//
 
 
 
// This source file is free software; you can redistribute it   
 
 
// and/or modify it under the terms of the GNU Lesser General   
 
 
// Public License as published by the Free Software Foundation; 
 
 
// either version 2.1 of the License, or (at your option) any   
 
 
// later version.
 
 
 
//
 
 
 
// This source is distributed in the hope that it will be       
 
 
// useful, but WITHOUT ANY WARRANTY; without even the implied   
 
 
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
 
 
// PURPOSE.  See the GNU Lesser General Public License for more 
 
 
// details.
 
 
 
//
 
 
 
// You should have received a copy of the GNU Lesser General    
 
 
// Public License along with this source; if not, write to the 
 
 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
 
 
// Boston, MA  02111-1307  USA
 
 
 
//-----------------------------------------------------------------
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// Module:
 
// Module:
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
module soc
 
module soc
Line 8... Line 44... 
    clk_i,
 
    clk_i,
 
    rst_i,
 
    rst_i,
 
    ext_intr_i,
 
    ext_intr_i,
 
    intr_o,
 
    intr_o,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
    // Memory interface
 
    // Memory interface
 
    io_addr_i,
 
    io_addr_i,
 
    io_data_i,
 
    io_data_i,
 
    io_data_o,
 
    io_data_o,
 
    io_wr_i,
 
    io_we_i,
 
    io_rd_i
 
    io_stb_i,
 
 
 
    io_ack_o
 
);
 
);
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// Params
 
// Params
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
parameter  [31:0]   CLK_KHZ              = 12288;
 
parameter  [31:0]   CLK_KHZ              = 12288;
 
parameter  [31:0]   UART_BAUD            = 115200;
 
 
 
parameter  [31:0]   SPI_FLASH_CLK_KHZ    = (12288/2);
 
 
 
parameter           SD_CLK_KHZ           = 8000;
 
 
 
parameter  [31:0]   EXTERNAL_INTERRUPTS  = 1;
 
parameter  [31:0]   EXTERNAL_INTERRUPTS  = 1;
 
parameter           SYSTICK_INTR_MS      = 1;
 
parameter           SYSTICK_INTR_MS      = 1;
 
parameter           ENABLE_SYSTICK_TIMER = "ENABLED";
 
parameter           ENABLE_SYSTICK_TIMER = "ENABLED";
 
parameter           ENABLE_HIGHRES_TIMER = "ENABLED";
 
parameter           ENABLE_HIGHRES_TIMER = "ENABLED";
 
 
 
 
Line 44... Line 70... 
input                   clk_i /*verilator public*/;
 
input                   clk_i /*verilator public*/;
 
input                   rst_i /*verilator public*/;
 
input                   rst_i /*verilator public*/;
 
input [(EXTERNAL_INTERRUPTS - 1):0]  ext_intr_i /*verilator public*/;
 
input [(EXTERNAL_INTERRUPTS - 1):0]  ext_intr_i /*verilator public*/;
 
output                  intr_o /*verilator public*/;
 
output                  intr_o /*verilator public*/;
 
 
 
 
 
 
 
 
 
// Memory Port
 
// Memory Port
 
input [31:0]            io_addr_i /*verilator public*/;
 
input [31:0]            io_addr_i /*verilator public*/;
 
input [31:0]            io_data_i /*verilator public*/;
 
input [31:0]            io_data_i /*verilator public*/;
 
output [31:0]           io_data_o /*verilator public*/;
 
output [31:0]           io_data_o /*verilator public*/;
 
input [3:0]             io_wr_i /*verilator public*/;
 
input                   io_we_i /*verilator public*/;
 
input                   io_rd_i /*verilator public*/;
 
input                   io_stb_i /*verilator public*/;
 
 
 
output                  io_ack_o /*verilator public*/;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// Registers / Wires
 
// Registers / Wires
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
wire [7:0]         timer_addr;
 
wire [7:0]         timer_addr;
 
wire [31:0]        timer_data_o;
 
wire [31:0]        timer_data_o;
 
wire [31:0]        timer_data_i;
 
wire [31:0]        timer_data_i;
 
wire [3:0]         timer_wr;
 
wire               timer_we;
 
wire               timer_rd;
 
wire               timer_stb;
 
wire               timer_intr_systick;
 
wire               timer_intr_systick;
 
wire               timer_intr_hires;
 
wire               timer_intr_hires;
 
 
 
 
 
wire [7:0]         intr_addr;
 
wire [7:0]         intr_addr;
 
wire [31:0]        intr_data_o;
 
wire [31:0]        intr_data_o;
 
wire [31:0]        intr_data_i;
 
wire [31:0]        intr_data_i;
 
wire [3:0]         intr_wr;
 
wire               intr_we;
 
wire               intr_rd;
 
wire               intr_stb;
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// Peripheral Interconnect
 
// Peripheral Interconnect
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
soc_pif8
 
soc_pif8
Line 99... Line 110... 
    // I/O bus (from mem_mux)
 
    // I/O bus (from mem_mux)
 
    // 0x12000000 - 0x12FFFFFF
 
    // 0x12000000 - 0x12FFFFFF
 
    .io_addr_i(io_addr_i),
 
    .io_addr_i(io_addr_i),
 
    .io_data_i(io_data_i),
 
    .io_data_i(io_data_i),
 
    .io_data_o(io_data_o),
 
    .io_data_o(io_data_o),
 
    .io_wr_i(io_wr_i),
 
    .io_we_i(io_we_i),
 
    .io_rd_i(io_rd_i),
 
    .io_stb_i(io_stb_i),
 
 
 
    .io_ack_o(io_ack_o),
 
 
 
 
 
    // Peripherals
 
    // Peripherals
 
    // Unused = 0x12000000 - 0x120000FF
 
    // Unused = 0x12000000 - 0x120000FF
 
    .periph0_addr_o(/*open*/),
 
    .periph0_addr_o(/*open*/),
 
    .periph0_data_o(/*open*/),
 
    .periph0_data_o(/*open*/),
 
    .periph0_data_i(32'h00000000),
 
    .periph0_data_i(32'h00000000),
 
    .periph0_wr_o(/*open*/),
 
    .periph0_we_o(/*open*/),
 
    .periph0_rd_o(/*open*/),
 
    .periph0_stb_o(/*open*/),
 
 
 
 
 
    // Timer = 0x12000100 - 0x120001FF
 
    // Timer = 0x12000100 - 0x120001FF
 
    .periph1_addr_o(timer_addr),
 
    .periph1_addr_o(timer_addr),
 
    .periph1_data_o(timer_data_o),
 
    .periph1_data_o(timer_data_o),
 
    .periph1_data_i(timer_data_i),
 
    .periph1_data_i(timer_data_i),
 
    .periph1_wr_o(timer_wr),
 
    .periph1_we_o(timer_we),
 
    .periph1_rd_o(timer_rd),
 
    .periph1_stb_o(timer_stb),
 
 
 
 
 
    // Interrupt Controller = 0x12000200 - 0x120002FF
 
    // Interrupt Controller = 0x12000200 - 0x120002FF
 
    .periph2_addr_o(intr_addr),
 
    .periph2_addr_o(intr_addr),
 
    .periph2_data_o(intr_data_o),
 
    .periph2_data_o(intr_data_o),
 
    .periph2_data_i(intr_data_i),
 
    .periph2_data_i(intr_data_i),
 
    .periph2_wr_o(intr_wr),
 
    .periph2_we_o(intr_we),
 
    .periph2_rd_o(intr_rd),
 
    .periph2_stb_o(intr_stb),
 
 
 
 
 
    // Unused = 0x12000300 - 0x120003FF
 
    // Unused = 0x12000300 - 0x120003FF
 
    .periph3_addr_o(/*open*/),
 
    .periph3_addr_o(/*open*/),
 
    .periph3_data_o(/*open*/),
 
    .periph3_data_o(/*open*/),
 
    .periph3_data_i(32'h00000000),
 
    .periph3_data_i(32'h00000000),
 
    .periph3_wr_o(/*open*/),
 
    .periph3_we_o(/*open*/),
 
    .periph3_rd_o(/*open*/),
 
    .periph3_stb_o(/*open*/),
 
 
 
 
 
    // Unused = 0x12000400 - 0x120004FF
 
    // Unused = 0x12000400 - 0x120004FF
 
    .periph4_addr_o(/*open*/),
 
    .periph4_addr_o(/*open*/),
 
    .periph4_data_o(/*open*/),
 
    .periph4_data_o(/*open*/),
 
    .periph4_data_i(32'h00000000),
 
    .periph4_data_i(32'h00000000),
 
    .periph4_wr_o(/*open*/),
 
    .periph4_we_o(/*open*/),
 
    .periph4_rd_o(/*open*/),
 
    .periph4_stb_o(/*open*/),
 
 
 
 
 
    // Unused = 0x12000500 - 0x120005FF
 
    // Unused = 0x12000500 - 0x120005FF
 
    .periph5_addr_o(/*open*/),
 
    .periph5_addr_o(/*open*/),
 
    .periph5_data_o(/*open*/),
 
    .periph5_data_o(/*open*/),
 
    .periph5_data_i(32'h00000000),
 
    .periph5_data_i(32'h00000000),
 
    .periph5_wr_o(/*open*/),
 
    .periph5_we_o(/*open*/),
 
    .periph5_rd_o(/*open*/),
 
    .periph5_stb_o(/*open*/),
 
 
 
 
 
    // Unused = 0x12000600 - 0x120006FF
 
    // Unused = 0x12000600 - 0x120006FF
 
    .periph6_addr_o(/*open*/),
 
    .periph6_addr_o(/*open*/),
 
    .periph6_data_o(/*open*/),
 
    .periph6_data_o(/*open*/),
 
    .periph6_data_i(32'h00000000),
 
    .periph6_data_i(32'h00000000),
 
    .periph6_wr_o(/*open*/),
 
    .periph6_we_o(/*open*/),
 
    .periph6_rd_o(/*open*/),
 
    .periph6_stb_o(/*open*/),
 
 
 
 
 
    // Unused = 0x12000700 - 0x120007FF
 
    // Unused = 0x12000700 - 0x120007FF
 
    .periph7_addr_o(/*open*/),
 
    .periph7_addr_o(/*open*/),
 
    .periph7_data_o(/*open*/),
 
    .periph7_data_o(/*open*/),
 
    .periph7_data_i(32'h00000000),
 
    .periph7_data_i(32'h00000000),
 
    .periph7_wr_o(/*open*/),
 
    .periph7_we_o(/*open*/),
 
    .periph7_rd_o(/*open*/)
 
    .periph7_stb_o(/*open*/)
 
);
 
);
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// Memory master arbiter
 
 
 
//-----------------------------------------------------------------
 
 
 
 
 
 
 
//-----------------------------------------------------------------
 
 
 
// UART
 
 
 
//-----------------------------------------------------------------
 
 
 
 
 
 
 
//-----------------------------------------------------------------
 
 
 
// GPIO
 
 
 
//-----------------------------------------------------------------
 
 
 
 
 
 
 
//-----------------------------------------------------------------
 
 
 
// SPI Flash Master
 
 
 
//-----------------------------------------------------------------
 
 
 
 
 
 
 
//-----------------------------------------------------------------
 
 
 
// DMA
 
 
 
//-----------------------------------------------------------------
 
 
 
 
 
 
 
//-----------------------------------------------------------------
 
 
 
// SD
 
 
 
//-----------------------------------------------------------------
 
 
 
 
 
 
 
//-----------------------------------------------------------------
 
 
 
// Generic Register
 
 
 
//-----------------------------------------------------------------
 
 
 
 
 
 
 
//-----------------------------------------------------------------
 
 
 
// Timer
 
// Timer
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
timer_periph
 
timer_periph
 
#(
 
#(
 
    .CLK_KHZ(CLK_KHZ),
 
    .CLK_KHZ(CLK_KHZ),
Line 207... Line 191... 
    .intr_systick_o(timer_intr_systick),
 
    .intr_systick_o(timer_intr_systick),
 
    .intr_hires_o(timer_intr_hires),
 
    .intr_hires_o(timer_intr_hires),
 
    .addr_i(timer_addr),
 
    .addr_i(timer_addr),
 
    .data_o(timer_data_i),
 
    .data_o(timer_data_i),
 
    .data_i(timer_data_o),
 
    .data_i(timer_data_o),
 
    .wr_i(timer_wr),
 
    .we_i(timer_we),
 
    .rd_i(timer_rd)
 
    .stb_i(timer_stb)
 
);
 
);
 
 
 
 
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
// Interrupt Controller
 
// Interrupt Controller
 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
Line 242... Line 226... 
    .intr_ext_i(ext_intr_i),
 
    .intr_ext_i(ext_intr_i),
 
 
 
 
 
    .addr_i(intr_addr),
 
    .addr_i(intr_addr),
 
    .data_o(intr_data_i),
 
    .data_o(intr_data_i),
 
    .data_i(intr_data_o),
 
    .data_i(intr_data_o),
 
    .wr_i(intr_wr),
 
    .we_i(intr_we),
 
    .rd_i(intr_rd)
 
    .stb_i(intr_stb)
 
);
 
);
 
 
 
 
 
//-------------------------------------------------------------------
 
//-------------------------------------------------------------------
 
// Hooks for debug
 
// Hooks for debug
 
//-------------------------------------------------------------------
 
//-------------------------------------------------------------------

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