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//-----------------------------------------------------------------
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// AltOR32
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// Alternative Lightweight OpenRisc
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// V2.0
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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//
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// Email: admin@ultra-embedded.com
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//
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// License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module:
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// Module:
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module soc_pif8
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module soc_pif8
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(
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(
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// General - Clocking & Reset
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// General - Clocking & Reset
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clk_i,
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input clk_i,
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rst_i,
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input rst_i,
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// Peripherals
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// Peripherals
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periph0_addr_o,
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output [7:0] periph0_addr_o,
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periph0_data_o,
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output [31:0] periph0_data_o,
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periph0_data_i,
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input [31:0] periph0_data_i,
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periph0_wr_o,
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output reg periph0_we_o,
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periph0_rd_o,
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output reg periph0_stb_o,
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periph1_addr_o,
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periph1_data_o,
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output [7:0] periph1_addr_o,
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periph1_data_i,
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output [31:0] periph1_data_o,
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periph1_wr_o,
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input [31:0] periph1_data_i,
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periph1_rd_o,
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output reg periph1_we_o,
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periph2_addr_o,
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output reg periph1_stb_o,
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periph2_data_o,
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periph2_data_i,
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output [7:0] periph2_addr_o,
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periph2_wr_o,
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output [31:0] periph2_data_o,
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periph2_rd_o,
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input [31:0] periph2_data_i,
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periph3_addr_o,
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output reg periph2_we_o,
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periph3_data_o,
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output reg periph2_stb_o,
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periph3_data_i,
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periph3_wr_o,
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output [7:0] periph3_addr_o,
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periph3_rd_o,
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output [31:0] periph3_data_o,
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periph4_addr_o,
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input [31:0] periph3_data_i,
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periph4_data_o,
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output reg periph3_we_o,
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periph4_data_i,
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output reg periph3_stb_o,
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periph4_wr_o,
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periph4_rd_o,
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output [7:0] periph4_addr_o,
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periph5_addr_o,
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output [31:0] periph4_data_o,
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periph5_data_o,
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input [31:0] periph4_data_i,
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periph5_data_i,
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output reg periph4_we_o,
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periph5_wr_o,
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output reg periph4_stb_o,
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periph5_rd_o,
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periph6_addr_o,
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output [7:0] periph5_addr_o,
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periph6_data_o,
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output [31:0] periph5_data_o,
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periph6_data_i,
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input [31:0] periph5_data_i,
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periph6_wr_o,
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output reg periph5_we_o,
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periph6_rd_o,
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output reg periph5_stb_o,
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periph7_addr_o,
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periph7_data_o,
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output [7:0] periph6_addr_o,
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periph7_data_i,
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output [31:0] periph6_data_o,
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periph7_wr_o,
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input [31:0] periph6_data_i,
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periph7_rd_o,
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output reg periph6_we_o,
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output reg periph6_stb_o,
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output [7:0] periph7_addr_o,
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output [31:0] periph7_data_o,
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input [31:0] periph7_data_i,
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output reg periph7_we_o,
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output reg periph7_stb_o,
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// I/O bus
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// I/O bus
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io_addr_i,
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input [31:0] io_addr_i,
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io_data_i,
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input [31:0] io_data_i,
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io_data_o,
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output reg [31:0] io_data_o,
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io_wr_i,
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input io_we_i,
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io_rd_i
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input io_stb_i,
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output reg io_ack_o
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// I/O
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// Memory Map
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//-----------------------------------------------------------------
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input clk_i /*verilator public*/;
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input rst_i /*verilator public*/;
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input [31:0] io_addr_i /*verilator public*/;
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output [31:0] io_data_o /*verilator public*/;
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input [31:0] io_data_i /*verilator public*/;
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input [3:0] io_wr_i /*verilator public*/;
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input io_rd_i /*verilator public*/;
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output [7:0] periph0_addr_o /*verilator public*/;
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output [31:0] periph0_data_o /*verilator public*/;
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input [31:0] periph0_data_i /*verilator public*/;
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output [3:0] periph0_wr_o /*verilator public*/;
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output periph0_rd_o /*verilator public*/;
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output [7:0] periph1_addr_o /*verilator public*/;
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output [31:0] periph1_data_o /*verilator public*/;
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input [31:0] periph1_data_i /*verilator public*/;
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output [3:0] periph1_wr_o /*verilator public*/;
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output periph1_rd_o /*verilator public*/;
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output [7:0] periph2_addr_o /*verilator public*/;
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output [31:0] periph2_data_o /*verilator public*/;
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input [31:0] periph2_data_i /*verilator public*/;
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output [3:0] periph2_wr_o /*verilator public*/;
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output periph2_rd_o /*verilator public*/;
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output [7:0] periph3_addr_o /*verilator public*/;
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output [31:0] periph3_data_o /*verilator public*/;
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input [31:0] periph3_data_i /*verilator public*/;
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output [3:0] periph3_wr_o /*verilator public*/;
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output periph3_rd_o /*verilator public*/;
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output [7:0] periph4_addr_o /*verilator public*/;
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output [31:0] periph4_data_o /*verilator public*/;
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input [31:0] periph4_data_i /*verilator public*/;
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output [3:0] periph4_wr_o /*verilator public*/;
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output periph4_rd_o /*verilator public*/;
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output [7:0] periph5_addr_o /*verilator public*/;
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output [31:0] periph5_data_o /*verilator public*/;
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input [31:0] periph5_data_i /*verilator public*/;
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output [3:0] periph5_wr_o /*verilator public*/;
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output periph5_rd_o /*verilator public*/;
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output [7:0] periph6_addr_o /*verilator public*/;
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output [31:0] periph6_data_o /*verilator public*/;
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input [31:0] periph6_data_i /*verilator public*/;
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output [3:0] periph6_wr_o /*verilator public*/;
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output periph6_rd_o /*verilator public*/;
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output [7:0] periph7_addr_o /*verilator public*/;
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output [31:0] periph7_data_o /*verilator public*/;
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input [31:0] periph7_data_i /*verilator public*/;
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output [3:0] periph7_wr_o /*verilator public*/;
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output periph7_rd_o /*verilator public*/;
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//-----------------------------------------------------------------
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// Registers
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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reg [3:0] r_mem_sel;
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reg [31:0] io_data_o;
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// Route data / address to all peripherals
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assign periph0_addr_o = io_addr_i[7:0];
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assign periph0_data_o = io_data_i;
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assign periph1_addr_o = io_addr_i[7:0];
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assign periph1_data_o = io_data_i;
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assign periph2_addr_o = io_addr_i[7:0];
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assign periph2_data_o = io_data_i;
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assign periph3_addr_o = io_addr_i[7:0];
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assign periph3_data_o = io_data_i;
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assign periph4_addr_o = io_addr_i[7:0];
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assign periph4_data_o = io_data_i;
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assign periph5_addr_o = io_addr_i[7:0];
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assign periph5_data_o = io_data_i;
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assign periph6_addr_o = io_addr_i[7:0];
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assign periph6_data_o = io_data_i;
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assign periph7_addr_o = io_addr_i[7:0];
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assign periph7_data_o = io_data_i;
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reg [7:0] periph0_addr_o;
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// Select correct target
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reg [31:0] periph0_data_o;
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always @ *
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reg [3:0] periph0_wr_o;
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reg periph0_rd_o;
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reg [7:0] periph1_addr_o;
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reg [31:0] periph1_data_o;
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reg [3:0] periph1_wr_o;
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reg periph1_rd_o;
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reg [7:0] periph2_addr_o;
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reg [31:0] periph2_data_o;
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reg [3:0] periph2_wr_o;
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reg periph2_rd_o;
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reg [7:0] periph3_addr_o;
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reg [31:0] periph3_data_o;
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reg [3:0] periph3_wr_o;
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reg periph3_rd_o;
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reg [7:0] periph4_addr_o;
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reg [31:0] periph4_data_o;
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reg [3:0] periph4_wr_o;
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reg periph4_rd_o;
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reg [7:0] periph5_addr_o;
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reg [31:0] periph5_data_o;
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reg [3:0] periph5_wr_o;
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reg periph5_rd_o;
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reg [7:0] periph6_addr_o;
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reg [31:0] periph6_data_o;
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reg [3:0] periph6_wr_o;
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reg periph6_rd_o;
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reg [7:0] periph7_addr_o;
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reg [31:0] periph7_data_o;
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reg [3:0] periph7_wr_o;
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reg periph7_rd_o;
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//-----------------------------------------------------------------
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// Memory Map
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//-----------------------------------------------------------------
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always @ (io_addr_i or io_wr_i or io_rd_i or io_data_i)
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begin
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begin
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periph0_addr_o = 8'h00;
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periph0_we_o = 1'b0;
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periph0_wr_o = 4'b0000;
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periph0_stb_o = 1'b0;
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periph0_rd_o = 1'b0;
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periph1_we_o = 1'b0;
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periph0_data_o = 32'h00000000;
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periph1_stb_o = 1'b0;
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periph1_addr_o = 8'h00;
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periph2_we_o = 1'b0;
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periph1_wr_o = 4'b0000;
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periph2_stb_o = 1'b0;
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periph1_rd_o = 1'b0;
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periph3_we_o = 1'b0;
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periph1_data_o = 32'h00000000;
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periph3_stb_o = 1'b0;
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periph2_addr_o = 8'h00;
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periph4_we_o = 1'b0;
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periph2_wr_o = 4'b0000;
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periph4_stb_o = 1'b0;
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periph2_rd_o = 1'b0;
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periph5_we_o = 1'b0;
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periph2_data_o = 32'h00000000;
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periph5_stb_o = 1'b0;
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periph3_addr_o = 8'h00;
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periph6_we_o = 1'b0;
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periph3_wr_o = 4'b0000;
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periph6_stb_o = 1'b0;
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periph3_rd_o = 1'b0;
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periph7_we_o = 1'b0;
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periph3_data_o = 32'h00000000;
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periph7_stb_o = 1'b0;
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periph4_addr_o = 8'h00;
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periph4_wr_o = 4'b0000;
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periph4_rd_o = 1'b0;
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periph4_data_o = 32'h00000000;
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periph5_addr_o = 8'h00;
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periph5_wr_o = 4'b0000;
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periph5_rd_o = 1'b0;
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periph5_data_o = 32'h00000000;
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periph6_addr_o = 8'h00;
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periph6_wr_o = 4'b0000;
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periph6_rd_o = 1'b0;
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periph6_data_o = 32'h00000000;
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periph7_addr_o = 8'h00;
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periph7_wr_o = 4'b0000;
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periph7_rd_o = 1'b0;
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periph7_data_o = 32'h00000000;
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// Decode 4-bit peripheral select
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// Decode 4-bit peripheral select
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case (io_addr_i[11:8])
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case (io_addr_i[11:8])
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// Peripheral 0
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// Peripheral 0
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4'd 0 :
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4'd 0 :
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begin
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begin
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periph0_addr_o = io_addr_i[7:0];
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periph0_we_o = io_we_i;
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periph0_wr_o = io_wr_i;
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periph0_stb_o = io_stb_i;
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periph0_rd_o = io_rd_i;
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periph0_data_o = io_data_i;
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end
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end
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// Peripheral 1
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// Peripheral 1
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4'd 1 :
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4'd 1 :
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begin
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begin
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periph1_addr_o = io_addr_i[7:0];
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periph1_we_o = io_we_i;
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periph1_wr_o = io_wr_i;
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periph1_stb_o = io_stb_i;
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periph1_rd_o = io_rd_i;
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periph1_data_o = io_data_i;
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end
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end
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// Peripheral 2
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// Peripheral 2
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4'd 2 :
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4'd 2 :
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begin
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begin
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periph2_addr_o = io_addr_i[7:0];
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periph2_we_o = io_we_i;
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periph2_wr_o = io_wr_i;
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periph2_stb_o = io_stb_i;
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periph2_rd_o = io_rd_i;
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periph2_data_o = io_data_i;
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end
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end
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// Peripheral 3
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// Peripheral 3
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4'd 3 :
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4'd 3 :
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begin
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begin
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periph3_addr_o = io_addr_i[7:0];
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periph3_we_o = io_we_i;
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periph3_wr_o = io_wr_i;
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periph3_stb_o = io_stb_i;
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periph3_rd_o = io_rd_i;
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periph3_data_o = io_data_i;
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end
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end
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// Peripheral 4
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// Peripheral 4
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4'd 4 :
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4'd 4 :
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begin
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begin
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periph4_addr_o = io_addr_i[7:0];
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periph4_we_o = io_we_i;
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periph4_wr_o = io_wr_i;
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periph4_stb_o = io_stb_i;
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periph4_rd_o = io_rd_i;
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periph4_data_o = io_data_i;
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end
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end
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// Peripheral 5
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// Peripheral 5
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4'd 5 :
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4'd 5 :
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begin
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begin
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periph5_addr_o = io_addr_i[7:0];
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periph5_we_o = io_we_i;
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periph5_wr_o = io_wr_i;
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periph5_stb_o = io_stb_i;
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periph5_rd_o = io_rd_i;
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periph5_data_o = io_data_i;
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end
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end
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// Peripheral 6
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// Peripheral 6
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4'd 6 :
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4'd 6 :
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begin
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begin
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periph6_addr_o = io_addr_i[7:0];
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periph6_we_o = io_we_i;
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periph6_wr_o = io_wr_i;
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periph6_stb_o = io_stb_i;
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periph6_rd_o = io_rd_i;
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periph6_data_o = io_data_i;
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end
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end
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// Peripheral 7
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// Peripheral 7
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4'd 7 :
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4'd 7 :
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begin
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begin
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periph7_addr_o = io_addr_i[7:0];
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periph7_we_o = io_we_i;
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periph7_wr_o = io_wr_i;
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periph7_stb_o = io_stb_i;
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periph7_rd_o = io_rd_i;
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periph7_data_o = io_data_i;
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end
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end
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default :
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default :
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;
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;
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endcase
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endcase
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end
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end
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Read Port
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// Read Port
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ *
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always @ (posedge clk_i or posedge rst_i)
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begin
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begin
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case (r_mem_sel)
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if (rst_i == 1'b1)
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// Peripheral 0
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4'd 0 :
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begin
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begin
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io_data_o = periph0_data_i;
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io_data_o <= 32'b0;
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io_ack_o <= 1'b0;
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end
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end
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// Peripheral 1
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else
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4'd 1 :
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begin
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begin
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io_data_o = periph1_data_i;
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if (io_stb_i)
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end
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// Peripheral 2
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4'd 2 :
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begin
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begin
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io_data_o = periph2_data_i;
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// Decode 4-bit peripheral select
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end
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case (io_addr_i[11:8])
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// Peripheral 0
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4'd 0 : io_data_o <= periph0_data_i;
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// Peripheral 1
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4'd 1 : io_data_o <= periph1_data_i;
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// Peripheral 2
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4'd 2 : io_data_o <= periph2_data_i;
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// Peripheral 3
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// Peripheral 3
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4'd 3 :
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4'd 3 : io_data_o <= periph3_data_i;
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begin
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io_data_o = periph3_data_i;
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end
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// Peripheral 4
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// Peripheral 4
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4'd 4 :
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4'd 4 : io_data_o <= periph4_data_i;
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begin
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io_data_o = periph4_data_i;
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end
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// Peripheral 5
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// Peripheral 5
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4'd 5 :
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4'd 5 : io_data_o <= periph5_data_i;
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begin
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io_data_o = periph5_data_i;
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end
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// Peripheral 6
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// Peripheral 6
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4'd 6 :
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4'd 6 : io_data_o <= periph6_data_i;
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begin
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io_data_o = periph6_data_i;
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end
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// Peripheral 7
|
// Peripheral 7
|
4'd 7 :
|
4'd 7 : io_data_o <= periph7_data_i;
|
begin
|
|
io_data_o = periph7_data_i;
|
|
end
|
|
|
|
default :
|
default : io_data_o <= 32'h00000000;
|
begin
|
|
io_data_o = 32'h00000000;
|
|
end
|
|
endcase
|
endcase
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
io_ack_o <= io_stb_i;
|
// Registered peripheral select
|
end
|
//-----------------------------------------------------------------
|
|
always @ (posedge clk_i or posedge rst_i)
|
|
begin
|
|
if (rst_i == 1'b1)
|
|
r_mem_sel <= 4'h0;
|
|
else
|
|
r_mem_sel <= io_addr_i[11:8];
|
|
end
|
end
|
|
|
endmodule
|
endmodule
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No newline at end of file
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No newline at end of file
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