| Line 77... |
Line 77... |
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# Select either the A23 or A25 core
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# Select either the A23 or A25 core
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ifdef A25
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ifdef A25
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AMBER_CORE = AMBER_A25_CORE
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AMBER_CORE = AMBER_A25_CORE
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else
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else
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AMBER_CORE =
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AMBER_CORE = AMBER_A23_CORE
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endif
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endif
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## FPGA type
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## FPGA type
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ifdef VIRTEX6
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ifdef VIRTEX6
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| Line 268... |
Line 268... |
# ----------------------------------------------------
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# ----------------------------------------------------
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# Note -iobuf YES is needed for the top-level verilog
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# Note -iobuf YES is needed for the top-level verilog
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# module synthesis
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# module synthesis
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$(WORK_FOLDER)/$(RTL_TOP).ngc : $(WORK_FOLDER)/run_id.txt $(XST_PROJ_FILE)
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$(WORK_FOLDER)/$(RTL_TOP).ngc : $(WORK_FOLDER)/run_id.txt write_config $(XST_PROJ_FILE)
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export XST_DESIGN=$(RTL_TOP)
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export XST_DESIGN=$(RTL_TOP)
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export XST_OFN=$(RTL_TOP)
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export XST_OFN=$(RTL_TOP)
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rm -Rf $(WORK_FOLDER)/$(RTL_TOP)xst $(WORK_FOLDER)/_ngo
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rm -Rf $(WORK_FOLDER)/$(RTL_TOP)xst $(WORK_FOLDER)/_ngo
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mkdir -p $(WORK_FOLDER)/$(RTL_TOP)xst/tmp $(WORK_FOLDER)/_ngo
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mkdir -p $(WORK_FOLDER)/$(RTL_TOP)xst/tmp $(WORK_FOLDER)/_ngo
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echo "work" > $(WORK_FOLDER)/$(RTL_TOP).lso
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echo "work" > $(WORK_FOLDER)/$(RTL_TOP).lso
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| Line 300... |
Line 300... |
test -e $(BITFILE_FOLDER) || mkdir $(BITFILE_FOLDER)
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test -e $(BITFILE_FOLDER) || mkdir $(BITFILE_FOLDER)
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echo 0 > $(WORK_FOLDER)/seed.txt
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echo 0 > $(WORK_FOLDER)/seed.txt
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date +%Y%m%d%H%M%S > $(WORK_FOLDER)/run_id.txt
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date +%Y%m%d%H%M%S > $(WORK_FOLDER)/run_id.txt
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$(BIN_FOLDER)/set_fpga_version.sh $(WORK_FOLDER)/run_id.txt
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$(BIN_FOLDER)/set_fpga_version.sh $(WORK_FOLDER)/run_id.txt
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$(MAKE) -C ../../../sw/boot-loader
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$(MAKE) -C ../../../sw/boot-loader
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# ----------------------------------------------------
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# Store the build configuration to a log file
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# ----------------------------------------------------
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write_config :
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@echo "work: $(WORK_FOLDER)" > $(LOG_FOLDER)/$(RTL_TOP).cfg.$(RUN_ID).txt
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@echo "$(XST_DEFINES)" >> $(LOG_FOLDER)/$(RTL_TOP).cfg.$(RUN_ID).txt
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