| Line 58... |
Line 58... |
VERILOG_INCLUDE_PATH = ../../vlog/lib ../../../sw/boot-loader
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VERILOG_INCLUDE_PATH = ../../vlog/lib ../../../sw/boot-loader
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# Name of top level verilog file (must be the same as its module name)
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# Name of top level verilog file (must be the same as its module name)
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RTL_TOP = system
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RTL_TOP = system
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# List of verilog source files
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XST_PROJ_FILE = source_files.prj
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# ----------------------------------------------------
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# ----------------------------------------------------
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# Build Configuration
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# Build Configuration
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# ----------------------------------------------------
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# ----------------------------------------------------
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| Line 88... |
Line 86... |
# Virtex-6 device
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# Virtex-6 device
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XILINX_FPGA = xc6vlx75tff784-3
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XILINX_FPGA = xc6vlx75tff784-3
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XST_DEFINES = XILINX_FPGA XILINX_VIRTEX6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=12
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XST_DEFINES = XILINX_FPGA XILINX_VIRTEX6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=12
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# Xilinx placement and timing constraints
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# Xilinx placement and timing constraints
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XST_CONST_FILE = xv6_constraints.ucf
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XST_CONST_FILE = xv6_constraints.ucf
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# List of verilog source files for Xilinx Virtex-6 device
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XST_PROJ_FILE = xv6_source_files.prj
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else
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else
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# The spartan6 device used on SP605 Development board
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# The spartan6 device used on SP605 Development board
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XILINX_FPGA = xc6slx45tfgg484-3
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XILINX_FPGA = xc6slx45tfgg484-3
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XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20
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XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20
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# Xilinx placement and timing constraints
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# Xilinx placement and timing constraints
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XST_CONST_FILE = xs6_constraints.ucf
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XST_CONST_FILE = xs6_constraints.ucf
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# List of verilog source files for Xilinx Spartan-6 device
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XST_PROJ_FILE = xs6_source_files.prj
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endif
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endif
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# ----------------------------------------------------
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# ----------------------------------------------------
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# Focus on speed or area
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# Focus on speed or area
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