| Line 69... |
Line 69... |
# AMBER_CLK_DIVIDER
|
# AMBER_CLK_DIVIDER
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# Sets the system clock frequency
|
# Sets the system clock frequency
|
# For Spartan-6 divide 800MHz by this number to get the frequency
|
# For Spartan-6 divide 800MHz by this number to get the frequency
|
# e.g. AMBER_CLK_DIVIDER=24
|
# e.g. AMBER_CLK_DIVIDER=24
|
# 800 MHz / 24 = 33.33 MHz
|
# 800 MHz / 24 = 33.33 MHz
|
# For Virtex-6 divide 1000MHz by this number to get the frequency
|
# For Virtex-6 divide 1200MHz by this number to get the frequency
|
|
|
# Select either the A23 or A25 core
|
# Select either the A23 or A25 core
|
ifdef A25
|
ifdef A25
|
AMBER_CORE = AMBER_A25_CORE
|
AMBER_CORE = AMBER_A25_CORE
|
else
|
else
|
| Line 83... |
Line 83... |
|
|
## FPGA type
|
## FPGA type
|
ifdef VIRTEX6
|
ifdef VIRTEX6
|
# Virtex-6 device
|
# Virtex-6 device
|
XILINX_FPGA = xc6vlx75tff784-3
|
XILINX_FPGA = xc6vlx75tff784-3
|
XST_DEFINES = XILINX_FPGA XILINX_VIRTEX6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=12
|
XST_DEFINES = XILINX_FPGA XILINX_VIRTEX6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=15
|
# Xilinx placement and timing constraints
|
# Xilinx placement and timing constraints
|
XST_CONST_FILE = xv6_constraints.ucf
|
XST_CONST_FILE = xv6_constraints.ucf
|
# List of verilog source files for Xilinx Virtex-6 device
|
# List of verilog source files for Xilinx Virtex-6 device
|
XST_PROJ_FILE = xv6_source_files.prj
|
XST_PROJ_FILE = xv6_source_files.prj
|
else
|
else
|
# The spartan6 device used on SP605 Development board
|
# The spartan6 device used on SP605 Development board
|
XILINX_FPGA = xc6slx45tfgg484-3
|
XILINX_FPGA = xc6slx45tfgg484-3
|
XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=18
|
XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20
|
# Xilinx placement and timing constraints
|
# Xilinx placement and timing constraints
|
XST_CONST_FILE = xs6_constraints.ucf
|
XST_CONST_FILE = xs6_constraints.ucf
|
# List of verilog source files for Xilinx Spartan-6 device
|
# List of verilog source files for Xilinx Spartan-6 device
|
XST_PROJ_FILE = xs6_source_files.prj
|
XST_PROJ_FILE = xs6_source_files.prj
|
endif
|
endif
|
| Line 242... |
Line 242... |
-t $(MAP_SEED) \
|
-t $(MAP_SEED) \
|
-w \
|
-w \
|
-ignore_keep_hierarchy \
|
-ignore_keep_hierarchy \
|
-detail \
|
-detail \
|
-timing \
|
-timing \
|
-register_duplication \
|
-register_duplication on \
|
-lc auto \
|
-lc auto \
|
-xe c -mt off -ir off \
|
-xe c -mt off -ir off \
|
-pr off -power off \
|
-pr off -power off \
|
-o $(RTL_TOP).map.ncd \
|
-o $(RTL_TOP).map.ncd \
|
$(RTL_TOP).ngd \
|
$(RTL_TOP).ngd \
|
