| Line 36... |
Line 36... |
# from http://www.opencores.org/lgpl.shtml //
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# from http://www.opencores.org/lgpl.shtml //
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# //
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# //
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# ----------------------------------------------------------------
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# ----------------------------------------------------------------
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|
|
# System
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# System
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verilog work ../../vlog/system/boot_mem.v
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verilog work ../../vlog/system/boot_mem32.v
|
|
verilog work ../../vlog/system/boot_mem128.v
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verilog work ../../vlog/system/clocks_resets.v
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verilog work ../../vlog/system/clocks_resets.v
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verilog work ../../vlog/system/interrupt_controller.v
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verilog work ../../vlog/system/interrupt_controller.v
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verilog work ../../vlog/system/system.v
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verilog work ../../vlog/system/system.v
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verilog work ../../vlog/system/test_module.v
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verilog work ../../vlog/system/test_module.v
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verilog work ../../vlog/system/timer_module.v
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verilog work ../../vlog/system/timer_module.v
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| Line 113... |
Line 114... |
verilog work ../../vlog/lib/xs6_addsub_n.v
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verilog work ../../vlog/lib/xs6_addsub_n.v
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verilog work ../../vlog/lib/xs6_sram_2048x32_byte_en.v
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verilog work ../../vlog/lib/xs6_sram_2048x32_byte_en.v
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verilog work ../../vlog/lib/xs6_sram_256x128_byte_en.v
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verilog work ../../vlog/lib/xs6_sram_256x128_byte_en.v
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verilog work ../../vlog/lib/xs6_sram_256x21_line_en.v
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verilog work ../../vlog/lib/xs6_sram_256x21_line_en.v
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verilog work ../../vlog/lib/xs6_sram_256x32_byte_en.v
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verilog work ../../vlog/lib/xs6_sram_256x32_byte_en.v
|
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verilog work ../../vlog/lib/xs6_sram_512x128_byte_en.v
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|
|
# Xilinx Spartan-6 DDR3 I/F
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# Xilinx Spartan-6 DDR3 I/F
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verilog work ../../vlog/xs6_ddr3/mcb_ddr3.v
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verilog work ../../vlog/xs6_ddr3/mcb_ddr3.v
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verilog work ../../vlog/xs6_ddr3/iodrp_controller.v
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verilog work ../../vlog/xs6_ddr3/iodrp_controller.v
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verilog work ../../vlog/xs6_ddr3/iodrp_mcb_controller.v
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verilog work ../../vlog/xs6_ddr3/iodrp_mcb_controller.v
|
