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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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*****************************************************************/
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*****************************************************************/
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#include "amber_registers.h"
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#include "amber_registers.h"
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#include "amber_macros.h"
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.section .text
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.section .text
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.globl main
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.globl main
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main:
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main:
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@ Run through the test 4 times
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@ 1 - cache off
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@ 2 - cache on but empty
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@ 3 - cache on and loaded
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@ 4 - same as 3
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mov r10, #4
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/* lsl 0 */
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/* lsl 0 */
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mov r1, #1
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1: mov r1, #1
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mov r2, r1, lsl #0
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mov r2, r1, lsl #0
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mov r3, #0x1
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expect r2, 1, __LINE__
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cmp r2, r3
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bne testfail
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/* lsl 1 */
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/* lsl 1 */
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mov r4, #1
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mov r4, #1
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mov r5, r4, lsl #1
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mov r5, r4, lsl #1
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mov r6, #2
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expect r5, 2, __LINE__
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cmp r5, r6
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bne testfail
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/* lsl 31 */
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/* lsl 31 */
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mov r7, #1
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mov r7, #1
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mov r8, r1, lsl #31
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mov r8, r1, lsl #31
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mov r9, #0x80000000
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expect r8, 0x80000000, __LINE__
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cmp r8, r9
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bne testfail
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/* lsr 1 */
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/* lsr 1 */
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mov r1, #2
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mov r1, #2
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mov r2, r1, lsr #1
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mov r2, r1, lsr #1
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mov r3, #0x1
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expect r2, 1, __LINE__
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cmp r2, r3
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bne testfail
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/* lsr 8 */
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/* lsr 8 */
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mov r4, #0xff00
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mov r4, #0xff00
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mov r5, r4, lsr #8
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mov r5, r4, lsr #8
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cmp r5, #0xff
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expect r5, 0xff, __LINE__
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bne testfail
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/* ror 8 */
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/* ror 8 */
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ldr r6, Data1
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ldr r6, Data1
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mov r7, r6, ror #8
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mov r7, r6, ror #8
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ldr r8, Data2
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ldr r8, Data2
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cmp r7, r8
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compare r7, r8, __LINE__
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bne testfail
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@ ---------------------
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@ Sequences of shift operations
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@ ---------------------
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@ lsl
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mov r0, #0
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mov r1, #1
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mov r2, #2
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mov r3, #3
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mov r4, #4
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mov r5, #5
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mov r6, r3, lsl #31
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mov r7, r0, lsl #2
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mov r8, r1, lsl #11
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mov r9, r2, lsl #17
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expect r6, 0x80000000, __LINE__
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expect r7, 0x00000000, __LINE__
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expect r8, 0x00000800, __LINE__
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expect r9, 0x00040000, __LINE__
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mov r6, r3, lsl #30
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mov r7, r1, lsl #2
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mov r8, r2, lsl #4
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mov r9, r3, lsl #5
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expect r6, 0xc0000000, __LINE__
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expect r7, 0x00000004, __LINE__
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expect r8, 0x00000020, __LINE__
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expect r9, 0x00000060, __LINE__
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@ lsr
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mov r0, #0x80000000
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mov r1, #0x7f000000
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mov r2, #0x80000001
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mov r3, #0x7fffffff
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mov r4, #0x7ffffffe
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mov r5, #0x55000000
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orr r5, r5, #0x55
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mov r6, r0, lsr #1
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mov r7, r0, lsr #2
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mov r8, r1, lsr #24
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mov r9, r2, lsr #1
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expect r6, 0x40000000, __LINE__
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expect r7, 0x20000000, __LINE__
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expect r8, 0x0000007f, __LINE__
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expect r9, 0x40000000, __LINE__
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@ ---------------------
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@ Enable the cache
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@ ---------------------
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mvn r0, #0
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mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area
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mov r0, #1
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mcr 15, 0, r0, cr2, cr0, 0 @ cache enable
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subs r10, r10, #1
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bne 1b
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b testpass
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b testpass
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testfail:
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testfail:
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