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[/] [amber/] [trunk/] [hw/] [tests/] [cache_flush.S] - Diff between revs 2 and 15
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Rev 2 |
Rev 15 |
Line 47... |
Line 47... |
main:
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main:
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@ ---------------------
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@ ---------------------
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@ Enable the cache
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@ Enable the cache
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@ ---------------------
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@ ---------------------
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mov r0, #0x00000001
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mov r0, #0x00000001
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mcr p15, 0, r0, c3, c0, 0 @ cacheable area
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mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area
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mov r0, #1
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mov r0, #1
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mcr p15, 0, r0, c2, c0, 0 @ cache enable
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mcr 15, 0, r0, cr2, cr0, 0 @ cache enable
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nop
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nop
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nop
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nop
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@ Write to a block of memory that straddles
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@ Write to a block of memory that straddles
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Line 81... |
Line 81... |
@ Flush the cache when the r7 loop count value is even
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@ Flush the cache when the r7 loop count value is even
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@ a write of any value to cp15, reg 1 will trigger a flush
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@ a write of any value to cp15, reg 1 will trigger a flush
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ands r8, r7, #1
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ands r8, r7, #1
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cmpeq r5, #21
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cmpeq r5, #21
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cmpne r5, #0x100
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cmpne r5, #0x100
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mcreq p15, 0, r0, c1, c0, 0 @ cache enable
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mcreq 15, 0, r0, cr1, cr0, 0 @ cache enable
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subs r5, r5, #1
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subs r5, r5, #1
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bne 2b
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bne 2b
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