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[/] [amber/] [trunk/] [hw/] [tests/] [cache_flush.S] - Diff between revs 2 and 15

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Rev 2 Rev 15
Line 47... Line 47...
main:
main:
        @ ---------------------
        @ ---------------------
        @ Enable the cache
        @ Enable the cache
        @ ---------------------
        @ ---------------------
        mov     r0,  #0x00000001
        mov     r0,  #0x00000001
        mcr     p15, 0, r0, c3, c0, 0   @ cacheable area
        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
        mov     r0,  #1
        mov     r0,  #1
        mcr     p15, 0, r0, c2, c0, 0   @ cache enable
        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
        nop
        nop
        nop
        nop
 
 
 
 
        @ Write to a block of memory that straddles
        @ Write to a block of memory that straddles
Line 81... Line 81...
        @ Flush the cache when the r7 loop count value is even
        @ Flush the cache when the r7 loop count value is even
        @ a write of any value to cp15, reg 1 will trigger a flush
        @ a write of any value to cp15, reg 1 will trigger a flush
        ands    r8, r7, #1
        ands    r8, r7, #1
        cmpeq   r5, #21
        cmpeq   r5, #21
        cmpne   r5, #0x100
        cmpne   r5, #0x100
        mcreq   p15, 0, r0, c1, c0, 0   @ cache enable
        mcreq   15, 0, r0, cr1, cr0, 0   @ cache enable
 
 
        subs    r5, r5, #1
        subs    r5, r5, #1
        bne     2b
        bne     2b
 
 
 
 

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