URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [tests/] [ethmac_reg.S] - Diff between revs 2 and 82

Rev 2	Rev 82
Line 70...	Line 70...
`str r5, [r4]`	`str r5, [r4]`

`@ Set MII address - device [4:0], register [12:8]`	`@ Set MII address - device [4:0], register [12:8]`
`ldr r4, AdrEthMacMIIAddress`	`ldr r4, AdrEthMacMIIAddress`
`mov r5, #0x07`	`mov r5, #0x07`
`orr r5, r5, #0x1600`
	`@ MII_BMSR register in eth_test.v has reg address of 1`
	`orr r5, r5, #0x0100`
`str r5, [r4]`	`str r5, [r4]`

`@ receive (read PHY register) Command`	`@ receive (read PHY register) Command`
`ldr r4, AdrEthMacMIICommand`	`ldr r4, AdrEthMacMIICommand`
`mov r5, #0x2`	`mov r5, #0x2`
Line 128...	Line 130...
`AdrEthMacMIITxData: .word ADR_ETHMAC_MIITXDATA`	`AdrEthMacMIITxData: .word ADR_ETHMAC_MIITXDATA`
`AdrEthMacMIIRxData: .word ADR_ETHMAC_MIIRXDATA`	`AdrEthMacMIIRxData: .word ADR_ETHMAC_MIIRXDATA`
`AdrEthMacMIIStatus: .word ADR_ETHMAC_MIISTATUS`	`AdrEthMacMIIStatus: .word ADR_ETHMAC_MIISTATUS`

`EthMacModerDefault: .word 0x0000a000`	`EthMacModerDefault: .word 0x0000a000`
`ExpectedMIIReadBack: .word 0x0000ffff`	`ExpectedMIIReadBack: .word 0x0000fe04 @ value from eth_test.v, state MD_TURN1`


`/* ========================================================================= */`	`/* ========================================================================= */`
`/* ========================================================================= */`	`/* ========================================================================= */`