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//////////////////////////////////////////////////////////////////
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// //
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// Arithmetic Logic Unit (ALU) for Amber 2 Core //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Supported functions: 32-bit add and subtract, AND, OR, //
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// XOR, NOT, Zero extent 8-bit numbers //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module a23_alu (
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input [31:0] i_a_in,
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input [31:0] i_b_in,
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input i_barrel_shift_carry,
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input i_status_bits_carry,
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input [8:0] i_function,
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output [31:0] o_out,
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output [3:0] o_flags
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);
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wire [31:0] a, b, b_not;
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wire [31:0] and_out, or_out, xor_out;
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wire [31:0] sign_ex8_out, sign_ex_16_out;
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wire [31:0] zero_ex8_out, zero_ex_16_out;
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wire [32:0] fadder_out;
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wire swap_sel;
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wire not_sel;
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wire [1:0] cin_sel;
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wire cout_sel;
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wire [3:0] out_sel;
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wire carry_in;
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wire carry_out;
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wire overflow_out;
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wire fadder_carry_out;
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assign { swap_sel, not_sel, cin_sel, cout_sel, out_sel } = i_function;
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// ========================================================
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// A Select
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// ========================================================
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assign a = (swap_sel ) ? i_b_in : i_a_in ;
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// ========================================================
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// B Select
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// ========================================================
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assign b = (swap_sel ) ? i_a_in : i_b_in ;
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// ========================================================
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// Not Select
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// ========================================================
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assign b_not = (not_sel ) ? ~b : b ;
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// ========================================================
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// Cin Select
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// ========================================================
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assign carry_in = (cin_sel==2'd0 ) ? 1'd0 :
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(cin_sel==2'd1 ) ? 1'd1 :
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i_status_bits_carry ; // add with carry
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// ========================================================
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// Cout Select
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// ========================================================
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assign carry_out = (cout_sel==1'd0 ) ? fadder_carry_out :
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i_barrel_shift_carry ;
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// For non-addition/subtractions that incorporate a shift
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// operation, C is set to the last bit
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// shifted out of the value by the shifter.
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// ========================================================
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// Overflow out
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// ========================================================
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// Only assert the overflow flag when using the adder
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assign overflow_out = out_sel == 4'd1 &&
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// overflow if adding two positive numbers and get a negative number
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( (!a[31] && !b_not[31] && fadder_out[31]) ||
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// or adding two negative numbers and get a positive number
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(a[31] && b_not[31] && !fadder_out[31]) );
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// ========================================================
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// ALU Operations
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// ========================================================
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`ifdef XILINX_FPGA
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// XIlinx Spartan 6 DSP module
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`ifdef XILINX_SPARTAN6_FPGA
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xs6_addsub_n #(.WIDTH(33))
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`endif
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`ifdef XILINX_VIRTEX6_FPGA
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xv6_addsub_n #(.WIDTH(33))
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`endif
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u_xx_addsub_33(
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.i_a ( {1'd0,a} ),
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.i_b ( {1'd0,b_not} ),
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.i_cin ( carry_in ),
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.i_sub ( 1'd0 ),
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.o_sum ( fadder_out ),
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.o_co ( )
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);
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`else
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assign fadder_out = { 1'd0,a} + {1'd0,b_not} + {32'd0,carry_in};
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`endif
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assign fadder_carry_out = fadder_out[32];
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assign and_out = a & b_not;
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assign or_out = a | b_not;
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assign xor_out = a ^ b_not;
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assign zero_ex8_out = {24'd0, b_not[7:0]};
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assign zero_ex_16_out = {16'd0, b_not[15:0]};
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assign sign_ex8_out = {{24{b_not[7]}}, b_not[7:0]};
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assign sign_ex_16_out = {{16{b_not[15]}}, b_not[15:0]};
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// ========================================================
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// Out Select
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// ========================================================
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assign o_out = out_sel == 4'd0 ? b_not :
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out_sel == 4'd1 ? fadder_out[31:0] :
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out_sel == 4'd2 ? zero_ex_16_out :
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out_sel == 4'd3 ? zero_ex8_out :
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out_sel == 4'd4 ? sign_ex_16_out :
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out_sel == 4'd5 ? sign_ex8_out :
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out_sel == 4'd6 ? xor_out :
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out_sel == 4'd7 ? or_out :
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and_out ;
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assign o_flags = { o_out[31], // negative
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|o_out == 1'd0, // zero
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carry_out, // carry
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overflow_out // overflow
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};
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endmodule
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