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//////////////////////////////////////////////////////////////////
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// //
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// L1 Cache for Amber 2 Core //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Synthesizable L1 Unified Data and Instruction Cache //
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// Cache is 4-way, 256 line and 16 bytes per line for //
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// a total of 16KB. The cache policy is write-through and //
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// read allocate. For swap instructions (SWP and SWPB) the //
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// location is evicted from the cache and read from main //
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// memory. //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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`include "a23_config_defines.v"
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module a23_cache
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#(
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// ---------------------------------------------------------
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// Cache Configuration
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// Limited to Linux 4k page sizes -> 256 lines
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parameter CACHE_LINES = 256,
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// This cannot be changed without some major surgeory on
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// this module
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parameter CACHE_WORDS_PER_LINE = 4,
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// Changing this parameter is the recommended
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// way to change the overall cache size; 2, 4 and 8 ways are supported.
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// 2 ways -> 8KB cache
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// 4 ways -> 16KB cache
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// 8 ways -> 32KB cache
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parameter WAYS = `A23_CACHE_WAYS ,
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// derived configuration parameters
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parameter CACHE_ADDR_WIDTH = log2 ( CACHE_LINES ), // = 8
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parameter WORD_SEL_WIDTH = log2 ( CACHE_WORDS_PER_LINE ), // = 2
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parameter TAG_ADDR_WIDTH = 32 - CACHE_ADDR_WIDTH - WORD_SEL_WIDTH - 2, // = 20
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parameter TAG_WIDTH = TAG_ADDR_WIDTH + 1, // = 21, including Valid flag
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parameter CACHE_LINE_WIDTH = CACHE_WORDS_PER_LINE * 32, // = 128
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parameter TAG_ADDR32_LSB = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2, // = 12
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parameter CACHE_ADDR32_MSB = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2 - 1, // = 11
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parameter CACHE_ADDR32_LSB = WORD_SEL_WIDTH + 2 , // = 4
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parameter WORD_SEL_MSB = WORD_SEL_WIDTH + 2 - 1, // = 3
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parameter WORD_SEL_LSB = 2 // = 2
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// ---------------------------------------------------------
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)
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(
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input i_clk,
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// Read / Write requests from core
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input i_select,
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input i_exclusive, // exclusive access, part of swap instruction
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input [31:0] i_write_data,
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input i_write_enable, // core issued write request
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input [31:0] i_address, // registered address from execute
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input [31:0] i_address_nxt, // un-registered version of address from execute stage
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input [3:0] i_byte_enable,
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input i_cache_enable, // from co-processor 15 configuration register
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input i_cache_flush, // from co-processor 15 register
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output [31:0] o_read_data,
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input i_core_stall,
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output o_stall,
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// WB Read Request
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output o_wb_req, // Read Request
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input [31:0] i_wb_address, // wb bus
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input [31:0] i_wb_read_data, // wb bus
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input i_wb_stall // wb_stb && !wb_ack
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);
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`include "a23_localparams.v"
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`include "a23_functions.v"
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// One-hot encoded
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localparam C_INIT = 0,
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C_CORE = 1,
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C_FILL = 2,
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C_INVA = 3,
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C_STATES = 4;
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localparam [3:0] CS_INIT = 4'd0,
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CS_IDLE = 4'd1,
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CS_FILL1 = 4'd2,
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CS_FILL2 = 4'd3,
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CS_FILL3 = 4'd4,
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CS_FILL4 = 4'd5,
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CS_FILL_COMPLETE = 4'd6,
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CS_TURN_AROUND = 4'd7,
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CS_WRITE_HIT1 = 4'd8,
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CS_EX_DELETE = 4'd9;
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reg [3:0] c_state = CS_IDLE;
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reg [C_STATES-1:0] source_sel = 1'd1 << C_CORE;
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reg [CACHE_ADDR_WIDTH:0] init_count = 'd0;
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wire [TAG_WIDTH-1:0] tag_rdata_way [WAYS-1:0];
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wire [CACHE_LINE_WIDTH-1:0] data_rdata_way[WAYS-1:0];
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wire [WAYS-1:0] data_wenable_way;
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wire [WAYS-1:0] data_hit_way;
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wire [WAYS-1:0] tag_wenable_way;
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reg [WAYS-1:0] select_way = 'd0;
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wire [WAYS-1:0] next_way;
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reg [WAYS-1:0] valid_bits_r = 'd0;
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reg [3:0] random_num = 4'hf;
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wire [CACHE_ADDR_WIDTH-1:0] tag_address;
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wire [TAG_WIDTH-1:0] tag_wdata;
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wire tag_wenable;
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wire [CACHE_LINE_WIDTH-1:0] read_miss_wdata;
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wire [CACHE_LINE_WIDTH-1:0] write_hit_wdata;
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wire [CACHE_LINE_WIDTH-1:0] data_wdata;
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wire [CACHE_ADDR_WIDTH-1:0] data_address;
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wire [31:0] write_data_word;
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wire hit;
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wire read_miss;
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wire write_miss;
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wire write_hit;
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reg [31:0] miss_address = 'd0;
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wire [CACHE_LINE_WIDTH-1:0] hit_rdata;
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wire write_stall;
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wire cache_busy_stall;
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wire read_stall;
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wire enable;
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wire [CACHE_ADDR_WIDTH-1:0] address;
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reg [CACHE_LINE_WIDTH-1:0] wb_rdata_burst = 'd0;
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reg wb_read_buf_valid = 'd0;
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reg [31:0] wb_read_buf_address = 'd0;
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reg [31:0] wb_read_buf_data = 'd0;
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wire wb_read_buf_hit;
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wire exclusive_access;
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wire ex_read_hit;
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reg ex_read_hit_r = 'd0;
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reg [WAYS-1:0] ex_read_hit_way = 'd0;
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reg [CACHE_ADDR_WIDTH-1:0] ex_read_address;
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wire ex_read_hit_clear;
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wire ex_read_cache_busy;
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genvar i;
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// ======================================
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// Address to use for cache access
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// ======================================
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// If currently stalled then the address for the next
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// cycle will be the same as it is in the current cycle
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//
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assign address = i_core_stall ? i_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
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i_address_nxt[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] ;
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// ======================================
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// Outputs
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// ======================================
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assign o_read_data = wb_read_buf_hit ? wb_read_buf_data :
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i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd0 ? hit_rdata [31:0] :
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i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd1 ? hit_rdata [63:32] :
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i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd2 ? hit_rdata [95:64] :
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hit_rdata [127:96] ;
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// Don't allow the cache to stall the wb i/f for an exclusive access
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// The cache needs a couple of cycles to flush a potential copy of the exclusive
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// address, but the wb can do the access in parallel. So there is no
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// stall in the state CS_EX_DELETE, even though the cache is out of action.
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// This works fine as long as the wb is stalling the core
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assign o_stall = read_stall || write_stall || cache_busy_stall || ex_read_cache_busy;
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assign o_wb_req = (( read_miss || write_miss ) && c_state == CS_IDLE ) ||
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c_state == CS_WRITE_HIT1;
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// ======================================
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// Cache State Machine
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// ======================================
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// Little State Machine to Flush Tag RAMS
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always @ ( posedge i_clk )
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if ( i_cache_flush )
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begin
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c_state <= C_INIT;
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source_sel <= 1'd1 << C_INIT;
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init_count <= 'd0;
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`ifdef A23_CACHE_DEBUG
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`TB_DEBUG_MESSAGE
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$display("Cache Flush");
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`endif
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end
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else
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case ( c_state )
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CS_INIT :
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if ( init_count < CACHE_LINES [CACHE_ADDR_WIDTH:0] )
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begin
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init_count <= init_count + 1'd1;
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source_sel <= 1'd1 << C_INIT;
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end
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else
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begin
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source_sel <= 1'd1 << C_CORE;
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c_state <= CS_TURN_AROUND;
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end
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CS_IDLE :
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begin
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source_sel <= 1'd1 << C_CORE;
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if ( ex_read_hit || ex_read_hit_r )
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begin
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select_way <= data_hit_way | ex_read_hit_way;
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c_state <= CS_EX_DELETE;
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source_sel <= 1'd1 << C_INVA;
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end
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else if ( read_miss )
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begin
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// wb read request asserted, wait for ack
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if ( !i_wb_stall )
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c_state <= CS_FILL1;
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end
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else if ( write_hit )
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c_state <= CS_WRITE_HIT1;
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end
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CS_FILL1 :
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begin
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// wb read request asserted, wait for ack
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if ( !i_wb_stall )
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c_state <= CS_FILL2;
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end
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CS_FILL2 :
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// first read of burst of 4
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// wb read request asserted, wait for ack
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if ( !i_wb_stall )
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c_state <= CS_FILL3;
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CS_FILL3 :
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// second read of burst of 4
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// wb read request asserted, wait for ack
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if ( !i_wb_stall )
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c_state <= CS_FILL4;
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CS_FILL4 :
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// third read of burst of 4
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// wb read request asserted, wait for ack
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if ( !i_wb_stall )
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begin
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c_state <= CS_FILL_COMPLETE;
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source_sel <= 1'd1 << C_FILL;
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// Pick a way to write the cache update into
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// Either pick one of the invalid caches, or if all are valid, then pick
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// one randomly
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select_way <= next_way;
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random_num <= {random_num[2], random_num[1], random_num[0],
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random_num[3]^random_num[2]};
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end
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// Write the read fetch data in this cycle
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CS_FILL_COMPLETE :
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// fourth read of burst of 4
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// wb read request asserted, wait for ack
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if ( !i_wb_stall )
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begin
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// Back to normal cache operations, but
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// use physical address for first read as
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// address moved before the stall was asserted for the read_miss
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// However don't use it if its a non-cached address!
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source_sel <= 1'd1 << C_CORE;
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c_state <= CS_TURN_AROUND;
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end
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// Ignore the tag read data in this cycle
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// Wait 1 cycle to pre-read the cache and return to normal operation
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CS_TURN_AROUND :
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begin
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c_state <= CS_IDLE;
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end
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// Flush the entry matching an exclusive access
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CS_EX_DELETE:
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begin
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`ifdef A23_CACHE_DEBUG
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`TB_DEBUG_MESSAGE
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$display("Cache deleted Locked entry");
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`endif
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c_state <= CS_TURN_AROUND;
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source_sel <= 1'd1 << C_CORE;
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end
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CS_WRITE_HIT1:
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begin
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// wait for an ack on the wb bus to complete the write
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if ( !i_wb_stall )
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c_state <= CS_IDLE;
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end
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endcase
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// ======================================
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// Capture WB Block Read - burst of 4 words
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// ======================================
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always @ ( posedge i_clk )
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if ( !i_wb_stall )
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wb_rdata_burst <= {i_wb_read_data, wb_rdata_burst[127:32]};
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// ======================================
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// WB Read Buffer
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// ======================================
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always @ ( posedge i_clk )
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begin
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if ( c_state == CS_FILL1 || c_state == CS_FILL2 ||
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c_state == CS_FILL3 || c_state == CS_FILL4 )
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begin
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if ( !i_wb_stall )
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begin
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wb_read_buf_valid <= 1'd1;
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wb_read_buf_address <= i_wb_address;
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wb_read_buf_data <= i_wb_read_data;
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end
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end
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else
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wb_read_buf_valid <= 1'd0;
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end
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// ======================================
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// Miss Address
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// ======================================
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always @ ( posedge i_clk )
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if ( o_wb_req )
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miss_address <= i_address;
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// ======================================
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// Remember Read-Modify-Write Hit
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// ======================================
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assign ex_read_hit_clear = c_state == CS_EX_DELETE;
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always @ ( posedge i_clk )
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if ( ex_read_hit_clear )
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begin
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ex_read_hit_r <= 1'd0;
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ex_read_hit_way <= 'd0;
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end
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else if ( ex_read_hit )
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begin
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`ifdef A23_CACHE_DEBUG
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`TB_DEBUG_MESSAGE
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$display ("Exclusive access cache hit address 0x%08h", i_address);
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`endif
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ex_read_hit_r <= 1'd1;
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ex_read_hit_way <= data_hit_way;
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end
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else if ( c_state == CS_FILL_COMPLETE && ex_read_hit_r )
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ex_read_hit_way <= select_way;
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always @ (posedge i_clk)
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if ( ex_read_hit )
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ex_read_address <= i_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB];
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assign tag_address = source_sel[C_FILL] ? miss_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
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source_sel[C_INVA] ? ex_read_address :
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source_sel[C_INIT] ? init_count[CACHE_ADDR_WIDTH-1:0] :
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source_sel[C_CORE] ? address :
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{CACHE_ADDR_WIDTH{1'd0}} ;
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assign data_address = write_hit ? i_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
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source_sel[C_FILL] ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
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source_sel[C_CORE] ? address :
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{CACHE_ADDR_WIDTH{1'd0}} ;
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assign tag_wdata = source_sel[C_FILL] ? {1'd1, miss_address[31:TAG_ADDR32_LSB]} :
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{TAG_WIDTH{1'd0}} ;
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// Data comes in off the WB bus in wrap4 with the missed data word first
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assign data_wdata = write_hit && c_state == CS_IDLE ? write_hit_wdata : read_miss_wdata;
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assign read_miss_wdata = miss_address[3:2] == 2'd0 ? wb_rdata_burst :
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miss_address[3:2] == 2'd1 ? { wb_rdata_burst[95:0], wb_rdata_burst[127:96] }:
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miss_address[3:2] == 2'd2 ? { wb_rdata_burst[63:0], wb_rdata_burst[127:64] }:
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{ wb_rdata_burst[31:0], wb_rdata_burst[127:32] };
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assign write_hit_wdata = i_address[3:2] == 2'd0 ? {hit_rdata[127:32], write_data_word } :
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i_address[3:2] == 2'd1 ? {hit_rdata[127:64], write_data_word, hit_rdata[31:0] } :
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i_address[3:2] == 2'd2 ? {hit_rdata[127:96], write_data_word, hit_rdata[63:0] } :
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{ write_data_word, hit_rdata[95:0] } ;
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|
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// Use Byte Enables
|
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assign write_data_word = i_byte_enable == 4'b0001 ? { o_read_data[31: 8], i_write_data[ 7: 0] } :
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i_byte_enable == 4'b0010 ? { o_read_data[31:16], i_write_data[15: 8], o_read_data[ 7:0]} :
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i_byte_enable == 4'b0100 ? { o_read_data[31:24], i_write_data[23:16], o_read_data[15:0]} :
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i_byte_enable == 4'b1000 ? { i_write_data[31:24], o_read_data[23:0]} :
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i_byte_enable == 4'b0011 ? { o_read_data[31:16], i_write_data[15: 0] } :
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i_byte_enable == 4'b1100 ? { i_write_data[31:16], o_read_data[15:0]} :
|
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i_write_data ;
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|
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|
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assign tag_wenable = source_sel[C_INVA] ? 1'd1 :
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source_sel[C_FILL] ? 1'd1 :
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source_sel[C_INIT] ? 1'd1 :
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source_sel[C_CORE] ? 1'd0 :
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1'd0 ;
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assign enable = i_select && i_cache_enable;
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assign exclusive_access = i_exclusive && i_cache_enable;
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|
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// the wb read buffer returns data directly from the wb bus to the
|
|
// core during a read miss operation
|
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assign wb_read_buf_hit = enable && wb_read_buf_address == i_address && wb_read_buf_valid;
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assign hit = |data_hit_way;
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assign write_hit = enable && i_write_enable && hit;
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assign write_miss = enable && i_write_enable && !hit && c_state != CS_WRITE_HIT1;
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|
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assign read_miss = enable && !i_write_enable && !(hit || wb_read_buf_hit);
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|
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// Exclusive read hit
|
|
assign ex_read_hit = exclusive_access && !i_write_enable && (hit || wb_read_buf_hit);
|
|
|
|
// Added to fix rare swap bug which occurs when the cache starts
|
|
// a fill just as the swap instruction starts to execute. The cache
|
|
// fails to check for a read hit on the swap read cycle.
|
|
// This signal stalls the core in that case until after the
|
|
// fill has completed.
|
|
assign ex_read_cache_busy = exclusive_access && !i_write_enable && c_state != CS_IDLE;
|
|
|
|
// Need to stall for a write miss to wait for the current wb
|
|
// read miss access to complete. Also for a write hit, need
|
|
// to stall for 1 cycle while the data cache is being written to
|
|
assign write_stall = ( write_hit && c_state != CS_WRITE_HIT1 ) ||
|
|
( write_miss && ( c_state != CS_IDLE ) ) ||
|
|
i_wb_stall ;
|
|
|
|
assign read_stall = read_miss;
|
|
|
|
// Core may or may not be trying to access cache memory during
|
|
// this phase of the read fetch. It could be doing e.g. a wb access
|
|
assign cache_busy_stall = ((c_state == CS_TURN_AROUND || c_state == CS_FILL1) && enable) ||
|
|
c_state == CS_INIT;
|
|
|
|
|
|
// ======================================
|
|
// Instantiate RAMS
|
|
// ======================================
|
|
|
|
generate
|
|
for ( i=0; i<WAYS;i=i+1 ) begin : rams
|
|
|
|
// Tag RAMs
|
|
`ifdef XILINX_SPARTAN6_FPGA
|
|
xs6_sram_256x21_line_en
|
|
`endif
|
|
|
|
`ifdef XILINX_VIRTEX6_FPGA
|
|
xv6_sram_256x21_line_en
|
|
`endif
|
|
|
|
`ifndef XILINX_FPGA
|
|
generic_sram_line_en
|
|
`endif
|
|
|
|
#(
|
|
.DATA_WIDTH ( TAG_WIDTH ),
|
|
.INITIALIZE_TO_ZERO ( 1 ),
|
|
.ADDRESS_WIDTH ( CACHE_ADDR_WIDTH ))
|
|
u_tag (
|
|
.i_clk ( i_clk ),
|
|
.i_write_data ( tag_wdata ),
|
|
.i_write_enable ( tag_wenable_way[i] ),
|
|
.i_address ( tag_address ),
|
|
|
|
.o_read_data ( tag_rdata_way[i] )
|
|
);
|
|
|
|
// Data RAMs
|
|
`ifdef XILINX_SPARTAN6_FPGA
|
|
xs6_sram_256x128_byte_en
|
|
`endif
|
|
|
|
`ifdef XILINX_VIRTEX6_FPGA
|
|
xv6_sram_256x128_byte_en
|
|
`endif
|
|
|
|
`ifndef XILINX_FPGA
|
|
generic_sram_byte_en
|
|
`endif
|
|
|
|
#(
|
|
.DATA_WIDTH ( CACHE_LINE_WIDTH) ,
|
|
.ADDRESS_WIDTH ( CACHE_ADDR_WIDTH) )
|
|
u_data (
|
|
.i_clk ( i_clk ),
|
|
.i_write_data ( data_wdata ),
|
|
.i_write_enable ( data_wenable_way[i] ),
|
|
.i_address ( data_address ),
|
|
.i_byte_enable ( {CACHE_LINE_WIDTH/8{1'd1}} ),
|
|
.o_read_data ( data_rdata_way[i] )
|
|
);
|
|
|
|
|
|
// Per tag-ram write-enable
|
|
assign tag_wenable_way[i] = tag_wenable && ( select_way[i] || source_sel[C_INIT] );
|
|
|
|
// Per data-ram write-enable
|
|
assign data_wenable_way[i] = (source_sel[C_FILL] && select_way[i]) ||
|
|
(write_hit && data_hit_way[i] && c_state == CS_IDLE);
|
|
// Per data-ram hit flag
|
|
assign data_hit_way[i] = tag_rdata_way[i][TAG_WIDTH-1] &&
|
|
tag_rdata_way[i][TAG_ADDR_WIDTH-1:0] == i_address[31:TAG_ADDR32_LSB] &&
|
|
c_state == CS_IDLE;
|
|
end
|
|
endgenerate
|
|
|
|
|
|
// ======================================
|
|
// Register Valid Bits
|
|
// ======================================
|
|
generate
|
|
if ( WAYS == 2 ) begin : valid_bits_2ways
|
|
|
|
always @ ( posedge i_clk )
|
|
if ( c_state == CS_IDLE )
|
|
valid_bits_r <= {tag_rdata_way[1][TAG_WIDTH-1],
|
|
tag_rdata_way[0][TAG_WIDTH-1]};
|
|
|
|
end
|
|
else if ( WAYS == 3 ) begin : valid_bits_3ways
|
|
|
|
always @ ( posedge i_clk )
|
|
if ( c_state == CS_IDLE )
|
|
valid_bits_r <= {tag_rdata_way[2][TAG_WIDTH-1],
|
|
tag_rdata_way[1][TAG_WIDTH-1],
|
|
tag_rdata_way[0][TAG_WIDTH-1]};
|
|
|
|
end
|
|
else if ( WAYS == 4 ) begin : valid_bits_4ways
|
|
|
|
always @ ( posedge i_clk )
|
|
if ( c_state == CS_IDLE )
|
|
valid_bits_r <= {tag_rdata_way[3][TAG_WIDTH-1],
|
|
tag_rdata_way[2][TAG_WIDTH-1],
|
|
tag_rdata_way[1][TAG_WIDTH-1],
|
|
tag_rdata_way[0][TAG_WIDTH-1]};
|
|
|
|
end
|
|
else begin : valid_bits_8ways
|
|
|
|
always @ ( posedge i_clk )
|
|
if ( c_state == CS_IDLE )
|
|
valid_bits_r <= {tag_rdata_way[7][TAG_WIDTH-1],
|
|
tag_rdata_way[6][TAG_WIDTH-1],
|
|
tag_rdata_way[5][TAG_WIDTH-1],
|
|
tag_rdata_way[4][TAG_WIDTH-1],
|
|
tag_rdata_way[3][TAG_WIDTH-1],
|
|
tag_rdata_way[2][TAG_WIDTH-1],
|
|
tag_rdata_way[1][TAG_WIDTH-1],
|
|
tag_rdata_way[0][TAG_WIDTH-1]};
|
|
|
|
end
|
|
endgenerate
|
|
|
|
|
|
// ======================================
|
|
// Select read hit data
|
|
// ======================================
|
|
generate
|
|
if ( WAYS == 2 ) begin : read_data_2ways
|
|
|
|
assign hit_rdata = data_hit_way[0] ? data_rdata_way[0] :
|
|
data_hit_way[1] ? data_rdata_way[1] :
|
|
{CACHE_LINE_WIDTH{1'd1}} ; // all 1's for debug
|
|
|
|
end
|
|
else if ( WAYS == 3 ) begin : read_data_3ways
|
|
|
|
assign hit_rdata = data_hit_way[0] ? data_rdata_way[0] :
|
|
data_hit_way[1] ? data_rdata_way[1] :
|
|
data_hit_way[2] ? data_rdata_way[2] :
|
|
{CACHE_LINE_WIDTH{1'd1}} ; // all 1's for debug
|
|
|
|
end
|
|
else if ( WAYS == 4 ) begin : read_data_4ways
|
|
|
|
assign hit_rdata = data_hit_way[0] ? data_rdata_way[0] :
|
|
data_hit_way[1] ? data_rdata_way[1] :
|
|
data_hit_way[2] ? data_rdata_way[2] :
|
|
data_hit_way[3] ? data_rdata_way[3] :
|
|
{CACHE_LINE_WIDTH{1'd1}} ; // all 1's for debug
|
|
|
|
end
|
|
else begin : read_data_8ways
|
|
|
|
assign hit_rdata = data_hit_way[0] ? data_rdata_way[0] :
|
|
data_hit_way[1] ? data_rdata_way[1] :
|
|
data_hit_way[2] ? data_rdata_way[2] :
|
|
data_hit_way[3] ? data_rdata_way[3] :
|
|
data_hit_way[4] ? data_rdata_way[4] :
|
|
data_hit_way[5] ? data_rdata_way[5] :
|
|
data_hit_way[6] ? data_rdata_way[6] :
|
|
data_hit_way[7] ? data_rdata_way[7] :
|
|
{CACHE_LINE_WIDTH{1'd1}} ; // all 1's for debug
|
|
|
|
end
|
|
endgenerate
|
|
|
|
|
|
// ======================================
|
|
// Function to select the way to use
|
|
// for fills
|
|
// ======================================
|
|
generate
|
|
if ( WAYS == 2 ) begin : pick_way_2ways
|
|
|
|
assign next_way = pick_way ( valid_bits_r, random_num );
|
|
|
|
function [WAYS-1:0] pick_way;
|
|
input [WAYS-1:0] valid_bits;
|
|
input [3:0] random_num;
|
|
begin
|
|
if ( valid_bits[0] == 1'd0 )
|
|
// way 0 not occupied so use it
|
|
pick_way = 2'b01;
|
|
else if ( valid_bits[1] == 1'd0 )
|
|
// way 1 not occupied so use it
|
|
pick_way = 2'b10;
|
|
else
|
|
begin
|
|
// All ways occupied so pick one randomly
|
|
case (random_num[3:1])
|
|
3'd0, 3'd3,
|
|
3'd5, 3'd6: pick_way = 2'b10;
|
|
default: pick_way = 2'b01;
|
|
endcase
|
|
end
|
|
end
|
|
endfunction
|
|
|
|
end
|
|
else if ( WAYS == 3 ) begin : pick_way_3ways
|
|
|
|
assign next_way = pick_way ( valid_bits_r, random_num );
|
|
|
|
function [WAYS-1:0] pick_way;
|
|
input [WAYS-1:0] valid_bits;
|
|
input [3:0] random_num;
|
|
begin
|
|
if ( valid_bits[0] == 1'd0 )
|
|
// way 0 not occupied so use it
|
|
pick_way = 3'b001;
|
|
else if ( valid_bits[1] == 1'd0 )
|
|
// way 1 not occupied so use it
|
|
pick_way = 3'b010;
|
|
else if ( valid_bits[2] == 1'd0 )
|
|
// way 2 not occupied so use it
|
|
pick_way = 3'b100;
|
|
else
|
|
begin
|
|
// All ways occupied so pick one randomly
|
|
case (random_num[3:1])
|
|
3'd0, 3'd1, 3'd2: pick_way = 3'b010;
|
|
3'd2, 3'd3, 3'd4: pick_way = 3'b100;
|
|
default: pick_way = 3'b001;
|
|
endcase
|
|
end
|
|
end
|
|
endfunction
|
|
|
|
end
|
|
else if ( WAYS == 4 ) begin : pick_way_4ways
|
|
|
|
assign next_way = pick_way ( valid_bits_r, random_num );
|
|
|
|
function [WAYS-1:0] pick_way;
|
|
input [WAYS-1:0] valid_bits;
|
|
input [3:0] random_num;
|
|
begin
|
|
if ( valid_bits[0] == 1'd0 )
|
|
// way 0 not occupied so use it
|
|
pick_way = 4'b0001;
|
|
else if ( valid_bits[1] == 1'd0 )
|
|
// way 1 not occupied so use it
|
|
pick_way = 4'b0010;
|
|
else if ( valid_bits[2] == 1'd0 )
|
|
// way 2 not occupied so use it
|
|
pick_way = 4'b0100;
|
|
else if ( valid_bits[3] == 1'd0 )
|
|
// way 3 not occupied so use it
|
|
pick_way = 4'b1000;
|
|
else
|
|
begin
|
|
// All ways occupied so pick one randomly
|
|
case (random_num[3:1])
|
|
3'd0, 3'd1: pick_way = 4'b0100;
|
|
3'd2, 3'd3: pick_way = 4'b1000;
|
|
3'd4, 3'd5: pick_way = 4'b0001;
|
|
default: pick_way = 4'b0010;
|
|
endcase
|
|
end
|
|
end
|
|
endfunction
|
|
|
|
end
|
|
else begin : pick_way_8ways
|
|
|
|
assign next_way = pick_way ( valid_bits_r, random_num );
|
|
|
|
function [WAYS-1:0] pick_way;
|
|
input [WAYS-1:0] valid_bits;
|
|
input [3:0] random_num;
|
|
begin
|
|
if ( valid_bits[0] == 1'd0 )
|
|
// way 0 not occupied so use it
|
|
pick_way = 8'b00000001;
|
|
else if ( valid_bits[1] == 1'd0 )
|
|
// way 1 not occupied so use it
|
|
pick_way = 8'b00000010;
|
|
else if ( valid_bits[2] == 1'd0 )
|
|
// way 2 not occupied so use it
|
|
pick_way = 8'b00000100;
|
|
else if ( valid_bits[3] == 1'd0 )
|
|
// way 3 not occupied so use it
|
|
pick_way = 8'b00001000;
|
|
else if ( valid_bits[4] == 1'd0 )
|
|
// way 3 not occupied so use it
|
|
pick_way = 8'b00010000;
|
|
else if ( valid_bits[5] == 1'd0 )
|
|
// way 3 not occupied so use it
|
|
pick_way = 8'b00100000;
|
|
else if ( valid_bits[6] == 1'd0 )
|
|
// way 3 not occupied so use it
|
|
pick_way = 8'b01000000;
|
|
else if ( valid_bits[7] == 1'd0 )
|
|
// way 3 not occupied so use it
|
|
pick_way = 8'b10000000;
|
|
else
|
|
begin
|
|
// All ways occupied so pick one randomly
|
|
case (random_num[3:1])
|
|
3'd0: pick_way = 8'b00010000;
|
|
3'd1: pick_way = 8'b00100000;
|
|
3'd2: pick_way = 8'b01000000;
|
|
3'd3: pick_way = 8'b10000000;
|
|
3'd4: pick_way = 8'b00000001;
|
|
3'd5: pick_way = 8'b00000010;
|
|
3'd6: pick_way = 8'b00000100;
|
|
default: pick_way = 8'b00001000;
|
|
endcase
|
|
end
|
|
end
|
|
endfunction
|
|
|
|
end
|
|
endgenerate
|
|
|
|
|
|
// ========================================================
|
|
// Debug WB bus - not synthesizable
|
|
// ========================================================
|
|
//synopsys translate_off
|
|
wire [(6*8)-1:0] xSOURCE_SEL;
|
|
wire [(20*8)-1:0] xC_STATE;
|
|
|
|
assign xSOURCE_SEL = source_sel[C_CORE] ? "C_CORE" :
|
|
source_sel[C_INIT] ? "C_INIT" :
|
|
source_sel[C_FILL] ? "C_FILL" :
|
|
source_sel[C_INVA] ? "C_INVA" :
|
|
"UNKNON" ;
|
|
|
|
assign xC_STATE = c_state == CS_INIT ? "CS_INIT" :
|
|
c_state == CS_IDLE ? "CS_IDLE" :
|
|
c_state == CS_FILL1 ? "CS_FILL1" :
|
|
c_state == CS_FILL2 ? "CS_FILL2" :
|
|
c_state == CS_FILL3 ? "CS_FILL3" :
|
|
c_state == CS_FILL4 ? "CS_FILL4" :
|
|
c_state == CS_FILL_COMPLETE ? "CS_FILL_COMPLETE" :
|
|
c_state == CS_EX_DELETE ? "CS_EX_DELETE" :
|
|
c_state == CS_TURN_AROUND ? "CS_TURN_AROUND" :
|
|
c_state == CS_WRITE_HIT1 ? "CS_WRITE_HIT1" :
|
|
"UNKNOWN" ;
|
|
|
|
|
|
generate
|
|
if ( WAYS == 2 ) begin : check_hit_2ways
|
|
|
|
always @( posedge i_clk )
|
|
if ( (data_hit_way[0] + data_hit_way[1] ) > 4'd1 )
|
|
begin
|
|
`TB_ERROR_MESSAGE
|
|
$display("Hit in more than one cache ways!");
|
|
end
|
|
|
|
end
|
|
else if ( WAYS == 3 ) begin : check_hit_3ways
|
|
|
|
always @( posedge i_clk )
|
|
if ( (data_hit_way[0] + data_hit_way[1] + data_hit_way[2] ) > 4'd1 )
|
|
begin
|
|
`TB_ERROR_MESSAGE
|
|
$display("Hit in more than one cache ways!");
|
|
end
|
|
|
|
end
|
|
else if ( WAYS == 4 ) begin : check_hit_4ways
|
|
|
|
always @( posedge i_clk )
|
|
if ( (data_hit_way[0] + data_hit_way[1] +
|
|
data_hit_way[2] + data_hit_way[3] ) > 4'd1 )
|
|
begin
|
|
`TB_ERROR_MESSAGE
|
|
$display("Hit in more than one cache ways!");
|
|
end
|
|
|
|
end
|
|
else if ( WAYS == 8 ) begin : check_hit_8ways
|
|
|
|
always @( posedge i_clk )
|
|
if ( (data_hit_way[0] + data_hit_way[1] +
|
|
data_hit_way[2] + data_hit_way[3] +
|
|
data_hit_way[4] + data_hit_way[5] +
|
|
data_hit_way[6] + data_hit_way[7] ) > 4'd1 )
|
|
begin
|
|
`TB_ERROR_MESSAGE
|
|
$display("Hit in more than one cache ways!");
|
|
end
|
|
|
|
end
|
|
else begin : check_hit_nways
|
|
|
|
initial
|
|
begin
|
|
`TB_ERROR_MESSAGE
|
|
$display("Unsupported number of ways %0d", WAYS);
|
|
$display("Set A23_CACHE_WAYS in a23_config_defines.v to either 2,3,4 or 8");
|
|
end
|
|
|
|
end
|
|
endgenerate
|
|
|
|
//synopsys translate_on
|
|
|
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
