| Line 66... |
Line 66... |
output reg [4:0] o_read_data_alignment = 1'd0, // 2 LSBs of read address used for calculating shift in LDRB ops
|
output reg [4:0] o_read_data_alignment = 1'd0, // 2 LSBs of read address used for calculating shift in LDRB ops
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|
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output reg [31:0] o_imm32 = 'd0,
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output reg [31:0] o_imm32 = 'd0,
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output reg [4:0] o_imm_shift_amount = 'd0,
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output reg [4:0] o_imm_shift_amount = 'd0,
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output reg o_shift_imm_zero = 'd0,
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output reg o_shift_imm_zero = 'd0,
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output reg [3:0] o_condition = 4'he, // 4'he = al
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output wire [3:0] o_condition,
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output reg o_exclusive_exec = 'd0, // exclusive access request ( swap instruction )
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output reg o_exclusive_exec = 'd0, // exclusive access request ( swap instruction )
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output reg o_data_access_exec = 'd0, // high means the memory access is a read
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output reg o_data_access_exec = 'd0, // high means the memory access is a read
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// read or write, low for instruction
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// read or write, low for instruction
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output reg [1:0] o_status_bits_mode = 2'b11, // SVC
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output wire [1:0] o_status_bits_mode,
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output reg o_status_bits_irq_mask = 1'd1,
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output wire o_status_bits_irq_mask,
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output reg o_status_bits_firq_mask = 1'd1,
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output wire o_status_bits_firq_mask,
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|
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output reg [3:0] o_rm_sel = 'd0,
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output reg [3:0] o_rm_sel = 'd0,
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output reg [3:0] o_rds_sel = 'd0,
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output reg [3:0] o_rds_sel = 'd0,
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output reg [3:0] o_rn_sel = 'd0,
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output reg [3:0] o_rn_sel = 'd0,
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output [3:0] o_rm_sel_nxt,
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output [3:0] o_rm_sel_nxt,
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| Line 87... |
Line 87... |
output reg [1:0] o_barrel_shift_function = 'd0,
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output reg [1:0] o_barrel_shift_function = 'd0,
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output reg [8:0] o_alu_function = 'd0,
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output reg [8:0] o_alu_function = 'd0,
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output reg o_use_carry_in = 'd0,
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output reg o_use_carry_in = 'd0,
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output reg [1:0] o_multiply_function = 'd0,
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output reg [1:0] o_multiply_function = 'd0,
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output reg [2:0] o_interrupt_vector_sel = 'd0,
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output reg [2:0] o_interrupt_vector_sel = 'd0,
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output reg [3:0] o_address_sel = 4'd2,
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output wire [3:0] o_address_sel,
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output reg [1:0] o_pc_sel = 2'd2,
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output wire [1:0] o_pc_sel,
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output reg [1:0] o_byte_enable_sel = 'd0, // byte, halfword or word write
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output reg [1:0] o_byte_enable_sel = 'd0, // byte, halfword or word write
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output reg [2:0] o_status_bits_sel = 'd0,
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output reg [2:0] o_status_bits_sel = 'd0,
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output reg [2:0] o_reg_write_sel,
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output reg [2:0] o_reg_write_sel,
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output reg o_user_mode_regs_load,
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output reg o_user_mode_regs_load,
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output reg o_user_mode_regs_store_nxt,
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output reg o_user_mode_regs_store_nxt,
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output reg o_firq_not_user_mode,
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output reg o_firq_not_user_mode,
|
|
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output reg o_write_data_wen = 'd0,
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output reg o_write_data_wen = 'd0,
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output reg o_base_address_wen = 'd0, // save LDM base address register
|
output reg o_base_address_wen = 'd0, // save LDM base address register
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// in case of data abort
|
// in case of data abort
|
output reg o_pc_wen = 1'd1,
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output wire o_pc_wen,
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output reg [14:0] o_reg_bank_wen = 'd0,
|
output reg [14:0] o_reg_bank_wen = 'd0,
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output reg [3:0] o_reg_bank_wsel = 'd0,
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output reg [3:0] o_reg_bank_wsel = 'd0,
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output reg o_status_bits_flags_wen = 'd0,
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output reg o_status_bits_flags_wen = 'd0,
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output reg o_status_bits_mode_wen = 'd0,
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output reg o_status_bits_mode_wen = 'd0,
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output reg o_status_bits_irq_mask_wen = 'd0,
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output reg o_status_bits_irq_mask_wen = 'd0,
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| Line 290... |
Line 290... |
|
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wire regop_set_flags;
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wire regop_set_flags;
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|
|
|
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// ========================================================
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// ========================================================
|
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// registers for output ports with non-zero initial values
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// ========================================================
|
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reg [3:0] condition_r = 4'he; // 4'he = al
|
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reg [1:0] status_bits_mode_r = 2'b11; // SVC
|
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reg status_bits_irq_mask_r = 1'd1;
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reg status_bits_firq_mask_r = 1'd1;
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reg [3:0] address_sel_r = 4'd2;
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reg [1:0] pc_sel_r = 2'd2;
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reg pc_wen_r = 1'd1;
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|
|
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assign o_condition = condition_r;
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assign o_status_bits_mode = status_bits_mode_r;
|
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assign o_status_bits_irq_mask = status_bits_irq_mask_r;
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assign o_status_bits_firq_mask = status_bits_firq_mask_r;
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assign o_address_sel = address_sel_r;
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assign o_pc_sel = pc_sel_r;
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assign o_pc_wen = pc_wen_r;
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|
|
|
|
|
|
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// ========================================================
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// Instruction Abort and Data Abort outputs
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// Instruction Abort and Data Abort outputs
|
// ========================================================
|
// ========================================================
|
|
|
assign o_iabt_trigger = instruction_iabt && o_status_bits_mode == SVC && control_state == INT_WAIT1;
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assign o_iabt_trigger = instruction_iabt && status_bits_mode_r == SVC && control_state == INT_WAIT1;
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assign o_iabt_address = instruction_address;
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assign o_iabt_address = instruction_address;
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assign o_iabt_status = instruction_iabt_status;
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assign o_iabt_status = instruction_iabt_status;
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|
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assign o_dabt_trigger = dabt_reg && !dabt_reg_d1;
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assign o_dabt_trigger = dabt_reg && !dabt_reg_d1;
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assign o_dabt_address = abt_address_reg;
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assign o_dabt_address = abt_address_reg;
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| Line 602... |
Line 623... |
always @*
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always @*
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begin
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begin
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// default mode
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// default mode
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status_bits_mode_nxt = i_execute_status_bits[1:0]; // change to mode in execute stage get reflected
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status_bits_mode_nxt = i_execute_status_bits[1:0]; // change to mode in execute stage get reflected
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// back to this stage automatically
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// back to this stage automatically
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status_bits_irq_mask_nxt = o_status_bits_irq_mask;
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status_bits_irq_mask_nxt = status_bits_irq_mask_r;
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status_bits_firq_mask_nxt = o_status_bits_firq_mask;
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status_bits_firq_mask_nxt = status_bits_firq_mask_r;
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exclusive_exec_nxt = 1'd0;
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exclusive_exec_nxt = 1'd0;
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data_access_exec_nxt = 1'd0;
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data_access_exec_nxt = 1'd0;
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copro_operation_nxt = 'd0;
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copro_operation_nxt = 'd0;
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|
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// Save an instruction to use later
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// Save an instruction to use later
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| Line 1375... |
Line 1396... |
// creates a 1 cycle gap with the old mode
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// creates a 1 cycle gap with the old mode
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// coming back from execute into instruction_decode
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// coming back from execute into instruction_decode
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// So squash that old mode value during this
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// So squash that old mode value during this
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// cycle of the interrupt transition
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// cycle of the interrupt transition
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if ( control_state == INT_WAIT1 )
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if ( control_state == INT_WAIT1 )
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status_bits_mode_nxt = o_status_bits_mode; // Supervisor mode
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status_bits_mode_nxt = status_bits_mode_r; // Supervisor mode
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|
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end
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end
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|
|
|
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// Speed up the long path from u_decode/o_read_data to u_register_bank/r8_firq
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// Speed up the long path from u_decode/o_read_data to u_register_bank/r8_firq
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| Line 1390... |
Line 1411... |
// ========================================================
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// ========================================================
|
// Next State Logic
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// Next State Logic
|
// ========================================================
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// ========================================================
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|
|
// this replicates the current value of the execute signal in the execute stage
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// this replicates the current value of the execute signal in the execute stage
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assign instruction_execute = conditional_execute ( o_condition, i_execute_status_bits[31:28] );
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assign instruction_execute = conditional_execute ( condition_r, i_execute_status_bits[31:28] );
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|
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assign instruction_valid = (control_state == EXECUTE || control_state == PRE_FETCH_EXEC) ||
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assign instruction_valid = (control_state == EXECUTE || control_state == PRE_FETCH_EXEC) ||
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// when last instruction was multi-cycle instruction but did not execute
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// when last instruction was multi-cycle instruction but did not execute
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// because condition was false then act like you're in the execute state
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// because condition was false then act like you're in the execute state
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(!instruction_execute && (control_state == PC_STALL1 ||
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(!instruction_execute && (control_state == PC_STALL1 ||
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| Line 1540... |
Line 1561... |
o_read_data_alignment <= {i_execute_address[1:0], 3'd0};
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o_read_data_alignment <= {i_execute_address[1:0], 3'd0};
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abt_address_reg <= i_execute_address;
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abt_address_reg <= i_execute_address;
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iabt_reg <= i_iabt;
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iabt_reg <= i_iabt;
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adex_reg <= i_adex;
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adex_reg <= i_adex;
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abt_status_reg <= i_abt_status;
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abt_status_reg <= i_abt_status;
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o_status_bits_mode <= status_bits_mode_nxt;
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status_bits_mode_r <= status_bits_mode_nxt;
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o_status_bits_irq_mask <= status_bits_irq_mask_nxt;
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status_bits_irq_mask_r <= status_bits_irq_mask_nxt;
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o_status_bits_firq_mask <= status_bits_firq_mask_nxt;
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status_bits_firq_mask_r <= status_bits_firq_mask_nxt;
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o_imm32 <= imm32_nxt;
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o_imm32 <= imm32_nxt;
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o_imm_shift_amount <= imm_shift_amount_nxt;
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o_imm_shift_amount <= imm_shift_amount_nxt;
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o_shift_imm_zero <= shift_imm_zero_nxt;
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o_shift_imm_zero <= shift_imm_zero_nxt;
|
|
|
// when have an interrupt, execute the interrupt operation
|
// when have an interrupt, execute the interrupt operation
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// unconditionally in the execute stage
|
// unconditionally in the execute stage
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// ensures that status_bits register gets updated correctly
|
// ensures that status_bits register gets updated correctly
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// Likewise when in middle of multi-cycle instructions
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// Likewise when in middle of multi-cycle instructions
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// execute them unconditionally
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// execute them unconditionally
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o_condition <= instruction_valid && !interrupt ? condition_nxt : AL;
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condition_r <= instruction_valid && !interrupt ? condition_nxt : AL;
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o_exclusive_exec <= exclusive_exec_nxt;
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o_exclusive_exec <= exclusive_exec_nxt;
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o_data_access_exec <= data_access_exec_nxt;
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o_data_access_exec <= data_access_exec_nxt;
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|
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o_rm_sel <= o_rm_sel_nxt;
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o_rm_sel <= o_rm_sel_nxt;
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o_rds_sel <= o_rds_sel_nxt;
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o_rds_sel <= o_rds_sel_nxt;
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| Line 1566... |
Line 1587... |
o_barrel_shift_function <= barrel_shift_function_nxt;
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o_barrel_shift_function <= barrel_shift_function_nxt;
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o_alu_function <= alu_function_nxt;
|
o_alu_function <= alu_function_nxt;
|
o_use_carry_in <= use_carry_in_nxt;
|
o_use_carry_in <= use_carry_in_nxt;
|
o_multiply_function <= multiply_function_nxt;
|
o_multiply_function <= multiply_function_nxt;
|
o_interrupt_vector_sel <= next_interrupt;
|
o_interrupt_vector_sel <= next_interrupt;
|
o_address_sel <= address_sel_nxt;
|
address_sel_r <= address_sel_nxt;
|
o_pc_sel <= pc_sel_nxt;
|
pc_sel_r <= pc_sel_nxt;
|
o_byte_enable_sel <= byte_enable_sel_nxt;
|
o_byte_enable_sel <= byte_enable_sel_nxt;
|
o_status_bits_sel <= status_bits_sel_nxt;
|
o_status_bits_sel <= status_bits_sel_nxt;
|
o_reg_write_sel <= reg_write_sel_nxt;
|
o_reg_write_sel <= reg_write_sel_nxt;
|
o_user_mode_regs_load <= user_mode_regs_load_nxt;
|
o_user_mode_regs_load <= user_mode_regs_load_nxt;
|
o_firq_not_user_mode <= firq_not_user_mode_nxt;
|
o_firq_not_user_mode <= firq_not_user_mode_nxt;
|
o_write_data_wen <= write_data_wen_nxt;
|
o_write_data_wen <= write_data_wen_nxt;
|
o_base_address_wen <= base_address_wen_nxt;
|
o_base_address_wen <= base_address_wen_nxt;
|
o_pc_wen <= pc_wen_nxt;
|
pc_wen_r <= pc_wen_nxt;
|
o_reg_bank_wsel <= reg_bank_wsel_nxt;
|
o_reg_bank_wsel <= reg_bank_wsel_nxt;
|
o_reg_bank_wen <= decode ( reg_bank_wsel_nxt );
|
o_reg_bank_wen <= decode ( reg_bank_wsel_nxt );
|
o_status_bits_flags_wen <= status_bits_flags_wen_nxt;
|
o_status_bits_flags_wen <= status_bits_flags_wen_nxt;
|
o_status_bits_mode_wen <= status_bits_mode_wen_nxt;
|
o_status_bits_mode_wen <= status_bits_mode_wen_nxt;
|
o_status_bits_irq_mask_wen <= status_bits_irq_mask_wen_nxt;
|
o_status_bits_irq_mask_wen <= status_bits_irq_mask_wen_nxt;
|
| Line 1642... |
Line 1663... |
if ( !i_fetch_stall )
|
if ( !i_fetch_stall )
|
begin
|
begin
|
irq <= i_irq;
|
irq <= i_irq;
|
firq <= i_firq;
|
firq <= i_firq;
|
|
|
if ( control_state == INT_WAIT1 && o_status_bits_mode == SVC )
|
if ( control_state == INT_WAIT1 && status_bits_mode_r == SVC )
|
begin
|
begin
|
dabt_reg <= 1'd0;
|
dabt_reg <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
| Line 1674... |
Line 1695... |
.i_instruction_execute ( instruction_execute ),
|
.i_instruction_execute ( instruction_execute ),
|
.i_instruction_address ( instruction_address ),
|
.i_instruction_address ( instruction_address ),
|
.i_interrupt ( {3{interrupt}} & next_interrupt ),
|
.i_interrupt ( {3{interrupt}} & next_interrupt ),
|
.i_interrupt_state ( control_state == INT_WAIT2 ),
|
.i_interrupt_state ( control_state == INT_WAIT2 ),
|
.i_instruction_undefined ( und_request ),
|
.i_instruction_undefined ( und_request ),
|
.i_pc_sel ( o_pc_sel ),
|
.i_pc_sel ( pc_sel_r ),
|
.i_pc_wen ( o_pc_wen )
|
.i_pc_wen ( pc_wen_r ));
|
);
|
|
|
|
|
|
wire [(15*8)-1:0] xCONTROL_STATE;
|
wire [(15*8)-1:0] xCONTROL_STATE;
|
wire [(15*8)-1:0] xMODE;
|
wire [(15*8)-1:0] xMODE;
|
|
|
| Line 1711... |
Line 1732... |
control_state == SWAP_WAIT1 ? "SWAP_WAIT1" :
|
control_state == SWAP_WAIT1 ? "SWAP_WAIT1" :
|
control_state == SWAP_WAIT2 ? "SWAP_WAIT2" :
|
control_state == SWAP_WAIT2 ? "SWAP_WAIT2" :
|
control_state == COPRO_WAIT ? "COPRO_WAIT" :
|
control_state == COPRO_WAIT ? "COPRO_WAIT" :
|
"UNKNOWN " ;
|
"UNKNOWN " ;
|
|
|
assign xMODE = mode_name ( o_status_bits_mode );
|
assign xMODE = mode_name ( status_bits_mode_r );
|
|
|
always @( posedge i_clk )
|
always @( posedge i_clk )
|
if (control_state == EXECUTE && ((instruction[0] === 1'bx) || (instruction[31] === 1'bx)))
|
if (control_state == EXECUTE && ((instruction[0] === 1'bx) || (instruction[31] === 1'bx)))
|
begin
|
begin
|
`TB_ERROR_MESSAGE
|
`TB_ERROR_MESSAGE
|
