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[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] [a23_execute.v] - Diff between revs 88 and 89

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Rev 88 Rev 89
Line 55... Line 55...
                                                    // high means the memory access is a read 
                                                    // high means the memory access is a read 
                                                    // read or write, low for instruction
                                                    // read or write, low for instruction
 
 
output reg  [31:0]          o_copro_write_data = 'd0,
output reg  [31:0]          o_copro_write_data = 'd0,
output reg  [31:0]          o_write_data = 'd0,
output reg  [31:0]          o_write_data = 'd0,
output reg  [31:0]          o_address = 32'hdead_dead,
output wire [31:0]          o_address,
output reg                  o_adex = 'd0,           // Address Exception
output reg                  o_adex = 'd0,           // Address Exception
output reg                  o_address_valid = 'd0,  // Prevents the reset address value being a 
output reg                  o_address_valid = 'd0,  // Prevents the reset address value being a 
                                                    // wishbone access
                                                    // wishbone access
output      [31:0]          o_address_nxt,          // un-registered version of address to the 
output      [31:0]          o_address_nxt,          // un-registered version of address to the 
                                                    // cache rams address ports
                                                    // cache rams address ports
Line 198... Line 198...
wire [31:0]         alu_out_pc_filtered;
wire [31:0]         alu_out_pc_filtered;
wire                adex_nxt;
wire                adex_nxt;
 
 
wire                carry_in;
wire                carry_in;
 
 
 
reg  [31:0]         address_r = 32'hdead_dead;
 
 
 
 
// ========================================================
// ========================================================
// Status Bits in PC register
// Status Bits in PC register
// ========================================================
// ========================================================
assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && execute) ?
assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && execute) ?
Line 262... Line 264...
// ========================================================
// ========================================================
// Adders
// Adders
// ========================================================
// ========================================================
assign pc_plus4      = pc        + 32'd4;
assign pc_plus4      = pc        + 32'd4;
assign pc_minus4     = pc        - 32'd4;
assign pc_minus4     = pc        - 32'd4;
assign address_plus4 = o_address + 32'd4;
assign address_plus4 = address_r + 32'd4;
assign alu_plus4     = alu_out   + 32'd4;
assign alu_plus4     = alu_out   + 32'd4;
assign rn_plus4      = rn        + 32'd4;
assign rn_plus4      = rn        + 32'd4;
 
 
 
 
// ========================================================
// ========================================================
// Barrel Shift Amount Select
// Barrel Shift Amount Select
// ========================================================
// ========================================================
// An immediate shift value of 0 is translated into 32
// An immediate shift value of 0 is translated into 32
assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0                           :
assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0                           :
Line 454... Line 457...
    o_priviledged           <= priviledged_update             ? priviledged_nxt              : o_priviledged;
    o_priviledged           <= priviledged_update             ? priviledged_nxt              : o_priviledged;
    o_exclusive             <= exclusive_update               ? i_exclusive_exec             : o_exclusive;
    o_exclusive             <= exclusive_update               ? i_exclusive_exec             : o_exclusive;
    o_data_access           <= data_access_update             ? i_data_access_exec           : o_data_access;
    o_data_access           <= data_access_update             ? i_data_access_exec           : o_data_access;
    o_write_enable          <= write_enable_update            ? write_enable_nxt             : o_write_enable;
    o_write_enable          <= write_enable_update            ? write_enable_nxt             : o_write_enable;
    o_write_data            <= write_data_update              ? write_data_nxt               : o_write_data;
    o_write_data            <= write_data_update              ? write_data_nxt               : o_write_data;
    o_address               <= address_update                 ? o_address_nxt                : o_address;
    address_r               <= address_update                 ? o_address_nxt                : address_r;
    o_adex                  <= address_update                 ? adex_nxt                     : o_adex;
    o_adex                  <= address_update                 ? adex_nxt                     : o_adex;
    o_address_valid         <= address_update                 ? 1'd1                         : o_address_valid;
    o_address_valid         <= address_update                 ? 1'd1                         : o_address_valid;
    o_byte_enable           <= byte_enable_update             ? byte_enable_nxt              : o_byte_enable;
    o_byte_enable           <= byte_enable_update             ? byte_enable_nxt              : o_byte_enable;
    o_copro_write_data      <= copro_write_data_update        ? write_data_nxt               : o_copro_write_data;
    o_copro_write_data      <= copro_write_data_update        ? write_data_nxt               : o_copro_write_data;
 
 
Line 470... Line 473...
    status_bits_mode_rds    <= status_bits_mode_rds_nr;
    status_bits_mode_rds    <= status_bits_mode_rds_nr;
    status_bits_irq_mask    <= status_bits_irq_mask_update    ? status_bits_irq_mask_nxt     : status_bits_irq_mask;
    status_bits_irq_mask    <= status_bits_irq_mask_update    ? status_bits_irq_mask_nxt     : status_bits_irq_mask;
    status_bits_firq_mask   <= status_bits_firq_mask_update   ? status_bits_firq_mask_nxt    : status_bits_firq_mask;
    status_bits_firq_mask   <= status_bits_firq_mask_update   ? status_bits_firq_mask_nxt    : status_bits_firq_mask;
    end
    end
 
 
 
assign o_address = address_r;
 
 
 
 
// ========================================================
// ========================================================
// Instantiate Barrel Shift
// Instantiate Barrel Shift
// ========================================================
// ========================================================
 
 

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