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//////////////////////////////////////////////////////////////////
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// //
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// Execute stage of Amber 2 Core //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Executes instructions. Instantiates the register file, ALU //
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// multiplication unit and barrel shifter. This stage is //
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// relitively simple. All the complex stuff is done in the //
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// decode stage. //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module a23_execute (
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input i_clk,
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input [31:0] i_read_data,
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input [4:0] i_read_data_alignment, // 2 LSBs of address in [4:3], appended
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// with 3 zeros
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input [31:0] i_copro_read_data, // From Co-Processor, to either Register
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// or Memory
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input i_data_access_exec, // from Instruction Decode stage
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// high means the memory access is a read
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// read or write, low for instruction
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output reg [31:0] o_copro_write_data = 'd0,
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output reg [31:0] o_write_data = 'd0,
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output reg [31:0] o_address = 32'hdead_dead,
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output reg o_adex = 'd0, // Address Exception
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output reg o_address_valid = 'd0, // Prevents the reset address value being a
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// wishbone access
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output [31:0] o_address_nxt, // un-registered version of address to the
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// cache rams address ports
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output reg o_priviledged = 'd0, // Priviledged access
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output reg o_exclusive = 'd0, // swap access
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output reg o_write_enable = 'd0,
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output reg [3:0] o_byte_enable = 'd0,
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output reg o_data_access = 'd0, // To Fetch stage. high = data fetch,
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// low = instruction fetch
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output [31:0] o_status_bits, // Full PC will all status bits, but PC part zero'ed out
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output o_multiply_done,
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// --------------------------------------------------
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// Control signals from Instruction Decode stage
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// --------------------------------------------------
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input i_fetch_stall, // stall all stages of the cpu at the same time
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input [1:0] i_status_bits_mode,
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input i_status_bits_irq_mask,
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input i_status_bits_firq_mask,
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input [31:0] i_imm32,
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input [4:0] i_imm_shift_amount,
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input i_shift_imm_zero,
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input [3:0] i_condition,
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input i_exclusive_exec, // swap access
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input [3:0] i_rm_sel,
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input [3:0] i_rds_sel,
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input [3:0] i_rn_sel,
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input [1:0] i_barrel_shift_amount_sel,
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input [1:0] i_barrel_shift_data_sel,
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input [1:0] i_barrel_shift_function,
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input [8:0] i_alu_function,
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input [1:0] i_multiply_function,
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input [2:0] i_interrupt_vector_sel,
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input [3:0] i_address_sel,
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input [1:0] i_pc_sel,
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input [1:0] i_byte_enable_sel,
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input [2:0] i_status_bits_sel,
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input [2:0] i_reg_write_sel,
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input i_user_mode_regs_load,
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input i_user_mode_regs_store_nxt,
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input i_firq_not_user_mode,
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input i_write_data_wen,
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input i_base_address_wen, // save LDM base address register,
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// in case of data abort
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input i_pc_wen,
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input [14:0] i_reg_bank_wen,
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input i_status_bits_flags_wen,
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input i_status_bits_mode_wen,
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input i_status_bits_irq_mask_wen,
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input i_status_bits_firq_mask_wen,
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input i_copro_write_data_wen
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);
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`include "a23_localparams.v"
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`include "a23_functions.v"
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// ========================================================
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// Internal signals
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// ========================================================
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wire [31:0] write_data_nxt;
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wire [3:0] byte_enable_nxt;
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wire [31:0] pc_plus4;
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wire [31:0] pc_minus4;
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wire [31:0] address_plus4;
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wire [31:0] alu_plus4;
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wire [31:0] rn_plus4;
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wire [31:0] alu_out;
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wire [3:0] alu_flags;
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wire [31:0] rm;
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wire [31:0] rs;
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wire [31:0] rd;
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wire [31:0] rn;
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wire [31:0] pc;
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wire [31:0] pc_nxt;
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wire write_enable_nxt;
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wire [31:0] interrupt_vector;
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wire [7:0] shift_amount;
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wire [31:0] barrel_shift_in;
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wire [31:0] barrel_shift_out;
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wire barrel_shift_carry;
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wire [3:0] status_bits_flags_nxt;
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reg [3:0] status_bits_flags = 'd0;
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wire [1:0] status_bits_mode_nxt;
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reg [1:0] status_bits_mode = SVC;
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// one-hot encoded rs select
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wire [3:0] status_bits_mode_rds_oh_nxt;
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reg [3:0] status_bits_mode_rds_oh = 1'd1 << OH_SVC;
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wire status_bits_mode_rds_oh_update;
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wire status_bits_irq_mask_nxt;
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reg status_bits_irq_mask = 1'd1;
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wire status_bits_firq_mask_nxt;
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reg status_bits_firq_mask = 1'd1;
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wire execute; // high when condition execution is true
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wire [31:0] reg_write_nxt;
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wire pc_wen;
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wire [14:0] reg_bank_wen;
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wire [31:0] multiply_out;
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wire [1:0] multiply_flags;
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reg [31:0] base_address = 'd0; // Saves base address during LDM instruction in
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// case of data abort
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wire priviledged_nxt;
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wire priviledged_update;
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wire address_update;
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wire base_address_update;
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wire write_data_update;
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wire copro_write_data_update;
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wire byte_enable_update;
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wire data_access_update;
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wire write_enable_update;
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wire exclusive_update;
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wire status_bits_flags_update;
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wire status_bits_mode_update;
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wire status_bits_irq_mask_update;
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wire status_bits_firq_mask_update;
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wire [31:0] alu_out_pc_filtered;
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wire adex_nxt;
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// ========================================================
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// Status Bits in PC register
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// ========================================================
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assign o_status_bits = { status_bits_flags, // 31:28
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status_bits_irq_mask, // 7
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status_bits_firq_mask, // 6
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24'd0,
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status_bits_mode }; // 1:0 = mode
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// ========================================================
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// Status Bits Select
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// ========================================================
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assign status_bits_flags_nxt = i_status_bits_sel == 3'd0 ? alu_flags :
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i_status_bits_sel == 3'd1 ? alu_out [31:28] :
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i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28] :
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// 4 = update flags after a multiply operation
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{ multiply_flags, status_bits_flags[1:0] } ;
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assign status_bits_mode_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_mode :
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i_status_bits_sel == 3'd1 ? alu_out [1:0] :
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i_copro_read_data [1:0] ;
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// Used for the Rds output of register_bank - this special version of
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// status_bits_mode speeds up the critical path from status_bits_mode through the
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// register_bank, barrel_shifter and alu. It moves a mux needed for the
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// i_user_mode_regs_store_nxt signal back into the previous stage -
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// so its really part of the decode stage even though the logic is right here
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// In addition the signal is one-hot encoded to further speed up the logic
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assign status_bits_mode_rds_oh_nxt = i_user_mode_regs_store_nxt ? 1'd1 << OH_USR :
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status_bits_mode_update ? oh_status_bits_mode(status_bits_mode_nxt) :
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oh_status_bits_mode(status_bits_mode) ;
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assign status_bits_irq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask :
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i_status_bits_sel == 3'd1 ? alu_out [27] :
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i_copro_read_data [27] ;
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assign status_bits_firq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask :
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i_status_bits_sel == 3'd1 ? alu_out [26] :
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i_copro_read_data [26] ;
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// ========================================================
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// Adders
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// ========================================================
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assign pc_plus4 = pc + 32'd4;
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assign pc_minus4 = pc - 32'd4;
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assign address_plus4 = o_address + 32'd4;
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assign alu_plus4 = alu_out + 32'd4;
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assign rn_plus4 = rn + 32'd4;
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// ========================================================
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// Barrel Shift Amount Select
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// ========================================================
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// An immediate shift value of 0 is translated into 32
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assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0 :
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i_barrel_shift_amount_sel == 2'd1 ? rs[7:0] :
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i_barrel_shift_amount_sel == 2'd2 ? {3'd0, i_imm_shift_amount } :
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{3'd0, i_read_data_alignment } ;
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// ========================================================
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// Barrel Shift Data Select
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// ========================================================
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assign barrel_shift_in = i_barrel_shift_data_sel == 2'd0 ? i_imm32 :
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i_barrel_shift_data_sel == 2'd1 ? i_read_data :
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rm ;
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// ========================================================
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// Interrupt vector Select
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// ========================================================
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assign interrupt_vector = // Reset vector
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(i_interrupt_vector_sel == 3'd0) ? 32'h00000000 :
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// Data abort interrupt vector
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(i_interrupt_vector_sel == 3'd1) ? 32'h00000010 :
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// Fast interrupt vector
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(i_interrupt_vector_sel == 3'd2) ? 32'h0000001c :
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// Regular interrupt vector
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(i_interrupt_vector_sel == 3'd3) ? 32'h00000018 :
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// Prefetch abort interrupt vector
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(i_interrupt_vector_sel == 3'd5) ? 32'h0000000c :
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// Undefined instruction interrupt vector
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(i_interrupt_vector_sel == 3'd6) ? 32'h00000004 :
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// Software (SWI) interrupt vector
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(i_interrupt_vector_sel == 3'd7) ? 32'h00000008 :
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// Default is the address exception interrupt
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32'h00000014 ;
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// ========================================================
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// Address Select
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// ========================================================
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// If rd is the pc, then seperate the address bits from the status bits for
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// generating the next address to fetch
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assign alu_out_pc_filtered = pc_wen && i_pc_sel == 2'd1 ? pcf(alu_out) : alu_out;
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// if current instruction does not execute because it does not meet the condition
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// then address advances to next instruction
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assign o_address_nxt = (!execute) ? pc_plus4 :
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(i_address_sel == 4'd0) ? pc_plus4 :
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(i_address_sel == 4'd1) ? alu_out_pc_filtered :
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(i_address_sel == 4'd2) ? interrupt_vector :
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(i_address_sel == 4'd3) ? pc :
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(i_address_sel == 4'd4) ? rn :
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(i_address_sel == 4'd5) ? address_plus4 : // MTRANS address incrementer
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(i_address_sel == 4'd6) ? alu_plus4 : // MTRANS decrement after
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rn_plus4 ; // MTRANS increment before
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// Data accesses use 32-bit address space, but instruction
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// accesses are restricted to 26 bit space
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assign adex_nxt = |o_address_nxt[31:26] && !i_data_access_exec;
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// ========================================================
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// Program Counter Select
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// ========================================================
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// If current instruction does not execute because it does not meet the condition
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// then PC advances to next instruction
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assign pc_nxt = (!execute) ? pc_plus4 :
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i_pc_sel == 2'd0 ? pc_plus4 :
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i_pc_sel == 2'd1 ? alu_out :
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interrupt_vector ;
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// ========================================================
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// Register Write Select
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// ========================================================
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wire [31:0] save_int_pc;
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wire [31:0] save_int_pc_m4;
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assign save_int_pc = { status_bits_flags,
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status_bits_irq_mask,
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status_bits_firq_mask,
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pc[25:2],
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status_bits_mode };
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assign save_int_pc_m4 = { status_bits_flags,
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status_bits_irq_mask,
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status_bits_firq_mask,
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pc_minus4[25:2],
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status_bits_mode };
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assign reg_write_nxt = i_reg_write_sel == 3'd0 ? alu_out :
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// save pc to lr on an interrupt
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i_reg_write_sel == 3'd1 ? save_int_pc_m4 :
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// to update Rd at the end of Multiplication
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i_reg_write_sel == 3'd2 ? multiply_out :
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i_reg_write_sel == 3'd3 ? o_status_bits :
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i_reg_write_sel == 3'd5 ? i_copro_read_data : // mrc
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i_reg_write_sel == 3'd6 ? base_address :
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save_int_pc ;
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// ========================================================
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// Byte Enable Select
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// ========================================================
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assign byte_enable_nxt = i_byte_enable_sel == 2'd0 ? 4'b1111 : // word write
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i_byte_enable_sel == 2'd2 ? // halfword write
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( o_address_nxt[1] == 1'd0 ? 4'b0011 :
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4'b1100 ) :
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o_address_nxt[1:0] == 2'd0 ? 4'b0001 : // byte write
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o_address_nxt[1:0] == 2'd1 ? 4'b0010 :
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o_address_nxt[1:0] == 2'd2 ? 4'b0100 :
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4'b1000 ;
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// ========================================================
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// Write Data Select
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// ========================================================
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assign write_data_nxt = i_byte_enable_sel == 2'd0 ? rd :
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{4{rd[ 7:0]}} ;
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// ========================================================
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// Conditional Execution
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// ========================================================
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assign execute = conditional_execute ( i_condition, status_bits_flags );
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// allow the PC to increment to the next instruction when current
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// instruction does not execute
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assign pc_wen = i_pc_wen || !execute;
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// only update register bank if current instruction executes
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assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
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// ========================================================
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// Priviledged output flag
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// ========================================================
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// Need to look at status_bits_mode_nxt so switch to priviledged mode
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// at the same time as assert interrupt vector address
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assign priviledged_nxt = ( i_status_bits_mode_wen ? status_bits_mode_nxt : status_bits_mode ) != USR ;
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// ========================================================
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// Write Enable
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// ========================================================
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// This must be de-asserted when execute is fault
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assign write_enable_nxt = execute && i_write_data_wen;
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// ========================================================
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// Register Update
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// ========================================================
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assign priviledged_update = !i_fetch_stall;
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assign data_access_update = !i_fetch_stall && execute;
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assign write_enable_update = !i_fetch_stall;
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assign write_data_update = !i_fetch_stall && execute && i_write_data_wen;
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assign exclusive_update = !i_fetch_stall && execute;
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assign address_update = !i_fetch_stall;
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assign byte_enable_update = !i_fetch_stall && execute && i_write_data_wen;
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assign copro_write_data_update = !i_fetch_stall && execute && i_copro_write_data_wen;
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assign base_address_update = !i_fetch_stall && execute && i_base_address_wen;
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assign status_bits_flags_update = !i_fetch_stall && execute && i_status_bits_flags_wen;
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assign status_bits_mode_update = !i_fetch_stall && execute && i_status_bits_mode_wen;
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assign status_bits_mode_rds_oh_update = !i_fetch_stall;
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assign status_bits_irq_mask_update = !i_fetch_stall && execute && i_status_bits_irq_mask_wen;
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assign status_bits_firq_mask_update = !i_fetch_stall && execute && i_status_bits_firq_mask_wen;
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always @( posedge i_clk )
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begin
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o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged;
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o_exclusive <= exclusive_update ? i_exclusive_exec : o_exclusive;
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o_data_access <= data_access_update ? i_data_access_exec : o_data_access;
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o_write_enable <= write_enable_update ? write_enable_nxt : o_write_enable;
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o_write_data <= write_data_update ? write_data_nxt : o_write_data;
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o_address <= address_update ? o_address_nxt : o_address;
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o_adex <= address_update ? adex_nxt : o_adex;
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o_address_valid <= address_update ? 1'd1 : o_address_valid;
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o_byte_enable <= byte_enable_update ? byte_enable_nxt : o_byte_enable;
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o_copro_write_data <= copro_write_data_update ? write_data_nxt : o_copro_write_data;
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base_address <= base_address_update ? rn : base_address;
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status_bits_flags <= status_bits_flags_update ? status_bits_flags_nxt : status_bits_flags;
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status_bits_mode <= status_bits_mode_update ? status_bits_mode_nxt : status_bits_mode;
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status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt : status_bits_mode_rds_oh;
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status_bits_irq_mask <= status_bits_irq_mask_update ? status_bits_irq_mask_nxt : status_bits_irq_mask;
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status_bits_firq_mask <= status_bits_firq_mask_update ? status_bits_firq_mask_nxt : status_bits_firq_mask;
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end
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// ========================================================
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// Instantiate Barrel Shift
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// ========================================================
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a23_barrel_shift u_barrel_shift (
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.i_in ( barrel_shift_in ),
|
|
.i_carry_in ( status_bits_flags[1] ),
|
|
.i_shift_amount ( shift_amount ),
|
|
.i_shift_imm_zero ( i_shift_imm_zero ),
|
|
.i_function ( i_barrel_shift_function ),
|
|
|
|
.o_out ( barrel_shift_out ),
|
|
.o_carry_out ( barrel_shift_carry )
|
|
);
|
|
|
|
|
|
// ========================================================
|
|
// Instantiate ALU
|
|
// ========================================================
|
|
a23_alu u_alu (
|
|
.i_a_in ( rn ),
|
|
.i_b_in ( barrel_shift_out ),
|
|
.i_barrel_shift_carry ( barrel_shift_carry ),
|
|
.i_status_bits_carry ( status_bits_flags[1] ),
|
|
.i_function ( i_alu_function ),
|
|
|
|
.o_out ( alu_out ),
|
|
.o_flags ( alu_flags )
|
|
);
|
|
|
|
|
|
// ========================================================
|
|
// Instantiate Booth 64-bit Multiplier-Accumulator
|
|
// ========================================================
|
|
a23_multiply u_multiply (
|
|
.i_clk ( i_clk ),
|
|
.i_fetch_stall ( i_fetch_stall ),
|
|
.i_a_in ( rs ),
|
|
.i_b_in ( rm ),
|
|
.i_function ( i_multiply_function ),
|
|
.i_execute ( execute ),
|
|
.o_out ( multiply_out ),
|
|
.o_flags ( multiply_flags ), // [1] = N, [0] = Z
|
|
.o_done ( o_multiply_done )
|
|
);
|
|
|
|
|
|
// ========================================================
|
|
// Instantiate Register Bank
|
|
// ========================================================
|
|
a23_register_bank u_register_bank(
|
|
.i_clk ( i_clk ),
|
|
.i_fetch_stall ( i_fetch_stall ),
|
|
.i_rm_sel ( i_rm_sel ),
|
|
.i_rds_sel ( i_rds_sel ),
|
|
.i_rn_sel ( i_rn_sel ),
|
|
.i_pc_wen ( pc_wen ),
|
|
.i_reg_bank_wen ( reg_bank_wen ),
|
|
.i_pc ( pc_nxt[25:2] ),
|
|
.i_reg ( reg_write_nxt ),
|
|
.i_mode_idec ( i_status_bits_mode ),
|
|
.i_mode_exec ( status_bits_mode ),
|
|
|
|
.i_status_bits_flags ( status_bits_flags ),
|
|
.i_status_bits_irq_mask ( status_bits_irq_mask ),
|
|
.i_status_bits_firq_mask ( status_bits_firq_mask ),
|
|
|
|
// pre-encoded in decode stage to speed up long path
|
|
.i_firq_not_user_mode ( i_firq_not_user_mode ),
|
|
|
|
// use one-hot version for speed, combine with i_user_mode_regs_store
|
|
.i_mode_rds_exec ( status_bits_mode_rds_oh ),
|
|
|
|
.i_user_mode_regs_load ( i_user_mode_regs_load ),
|
|
.o_rm ( rm ),
|
|
.o_rs ( rs ),
|
|
.o_rd ( rd ),
|
|
.o_rn ( rn ),
|
|
.o_pc ( pc )
|
|
);
|
|
|
|
|
|
// ========================================================
|
|
// Debug - non-synthesizable code
|
|
// ========================================================
|
|
//synopsys translate_off
|
|
|
|
wire [(2*8)-1:0] xCONDITION;
|
|
wire [(4*8)-1:0] xMODE;
|
|
|
|
assign xCONDITION = i_condition == EQ ? "EQ" :
|
|
i_condition == NE ? "NE" :
|
|
i_condition == CS ? "CS" :
|
|
i_condition == CC ? "CC" :
|
|
i_condition == MI ? "MI" :
|
|
i_condition == PL ? "PL" :
|
|
i_condition == VS ? "VS" :
|
|
i_condition == VC ? "VC" :
|
|
i_condition == HI ? "HI" :
|
|
i_condition == LS ? "LS" :
|
|
i_condition == GE ? "GE" :
|
|
i_condition == LT ? "LT" :
|
|
i_condition == GT ? "GT" :
|
|
i_condition == LE ? "LE" :
|
|
i_condition == AL ? "AL" :
|
|
"NV " ;
|
|
|
|
assign xMODE = status_bits_mode == SVC ? "SVC" :
|
|
status_bits_mode == IRQ ? "IRQ" :
|
|
status_bits_mode == FIRQ ? "FIRQ" :
|
|
status_bits_mode == USR ? "USR" :
|
|
"XXX" ;
|
|
|
|
|
|
//synopsys translate_on
|
|
|
|
endmodule
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
