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//////////////////////////////////////////////////////////////////
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// //
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// Fetch - Instantiates the fetch stage sub-modules of //
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// the Amber 2 Core //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Instantiates the Cache and Wishbone I/F //
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// Also contains a little bit of logic to decode memory //
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// accesses to decide if they are cached or not //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module a23_fetch
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(
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input i_clk,
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input [31:0] i_address,
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input i_address_valid,
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input [31:0] i_address_nxt, // un-registered version of address to the cache rams
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input [31:0] i_write_data,
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input i_write_enable,
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output [31:0] o_read_data,
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input i_priviledged,
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input i_exclusive, // high for read part of swap access
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input [3:0] i_byte_enable,
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input i_data_access, // high for data petch, low for instruction fetch
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input i_cache_enable, // cache enable
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input i_cache_flush, // cache flush
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input [31:0] i_cacheable_area, // each bit corresponds to 2MB address space
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input i_system_rdy,
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output o_fetch_stall, // when this is asserted all registers
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// in all 3 pipeline stages are held
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// at their current values
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// Wishbone Master I/F
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output [31:0] o_wb_adr,
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output [3:0] o_wb_sel,
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output o_wb_we,
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input [31:0] i_wb_dat,
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output [31:0] o_wb_dat,
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output o_wb_cyc,
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output o_wb_stb,
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input i_wb_ack,
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input i_wb_err
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);
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`include "memory_configuration.v"
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wire cache_stall;
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wire wb_stall;
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wire [31:0] cache_read_data;
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wire sel_cache;
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wire sel_wb;
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wire cache_wb_req;
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wire address_cachable;
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// ======================================
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// Memory Decode
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// ======================================
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assign address_cachable = in_cachable_mem( i_address ) && i_cacheable_area[i_address[25:21]];
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assign sel_cache = address_cachable && i_address_valid && i_cache_enable && !i_exclusive;
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// Don't start wishbone transfers when the cache is stalling the core
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// The cache stalls the core during its initialization sequence
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assign sel_wb = !sel_cache && i_address_valid && !(cache_stall);
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// Return read data either from the wishbone bus or the cache
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assign o_read_data = sel_cache ? cache_read_data :
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sel_wb ? i_wb_dat :
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32'hffeeddcc ;
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// Stall the instruction decode and execute stages of the core
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// when the fetch stage needs more than 1 cycle to return the requested
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// read data
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assign o_fetch_stall = !i_system_rdy || wb_stall || cache_stall;
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// ======================================
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// L1 Cache (Unified Instruction and Data)
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// ======================================
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a23_cache u_cache (
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.i_clk ( i_clk ),
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.i_select ( sel_cache ),
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.i_exclusive ( i_exclusive ),
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.i_write_data ( i_write_data ),
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.i_write_enable ( i_write_enable ),
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.i_address ( i_address ),
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.i_address_nxt ( i_address_nxt ),
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.i_byte_enable ( i_byte_enable ),
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.i_cache_enable ( i_cache_enable ),
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.i_cache_flush ( i_cache_flush ),
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.o_read_data ( cache_read_data ),
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.o_stall ( cache_stall ),
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.i_core_stall ( o_fetch_stall ),
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.o_wb_req ( cache_wb_req ),
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.i_wb_address ( o_wb_adr ),
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.i_wb_read_data ( i_wb_dat ),
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.i_wb_stall ( o_wb_stb & ~i_wb_ack )
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);
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// ======================================
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// Wishbone Master I/F
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// ======================================
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a23_wishbone u_wishbone (
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// CPU Side
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.i_clk ( i_clk ),
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// Core Accesses to Wishbone bus
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.i_select ( sel_wb ),
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.i_write_data ( i_write_data ),
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.i_write_enable ( i_write_enable ),
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.i_byte_enable ( i_byte_enable ),
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.i_data_access ( i_data_access ),
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.i_exclusive ( i_exclusive ),
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.i_address ( i_address ),
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.o_stall ( wb_stall ),
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// Cache Accesses to Wishbone bus
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// L1 Cache enable - used for hprot
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.i_cache_req ( cache_wb_req ),
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.o_wb_adr ( o_wb_adr ),
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.o_wb_sel ( o_wb_sel ),
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.o_wb_we ( o_wb_we ),
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.i_wb_dat ( i_wb_dat ),
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.o_wb_dat ( o_wb_dat ),
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.o_wb_cyc ( o_wb_cyc ),
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.o_wb_stb ( o_wb_stb ),
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.i_wb_ack ( i_wb_ack ),
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.i_wb_err ( i_wb_err )
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);
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endmodule
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