| Line 102... |
Line 102... |
reg servicing_cache = 'd0;
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reg servicing_cache = 'd0;
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wire [3:0] byte_enable;
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wire [3:0] byte_enable;
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reg exclusive_access = 'd0;
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reg exclusive_access = 'd0;
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wire read_ack;
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wire read_ack;
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wire wait_write_ack;
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wire wait_write_ack;
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wire wb_wait;
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// Write buffer
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reg [31:0] wbuf_data_r = 'd0;
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reg [31:0] wbuf_addr_r = 'd0;
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reg [3:0] wbuf_sel_r = 'd0;
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reg wbuf_busy_r = 'd0;
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assign read_ack = !o_wb_we && i_wb_ack;
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assign read_ack = !o_wb_we && i_wb_ack;
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assign o_stall = ( core_read_request && !read_ack ) ||
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assign o_stall = ( core_read_request && !read_ack ) ||
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( core_read_request && servicing_cache ) ||
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( core_read_request && servicing_cache ) ||
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( core_write_request && servicing_cache ) ;
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( core_write_request && servicing_cache ) ||
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( core_write_request && wishbone_st == WB_WAIT_ACK) ||
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( cache_write_request && wishbone_st == WB_WAIT_ACK) ||
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wbuf_busy_r;
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// Don't stall on writes
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// Don't stall on writes
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// Wishbone is doing burst read so make core wait to execute the write
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// Wishbone is doing burst read so make core wait to execute the write
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// ( core_write_request && !i_wb_ack ) ;
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// ( core_write_request && !i_wb_ack ) ;
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| Line 120... |
Line 129... |
assign core_write_request = i_select && i_write_enable;
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assign core_write_request = i_select && i_write_enable;
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assign cache_read_request = i_cache_req && !i_write_enable;
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assign cache_read_request = i_cache_req && !i_write_enable;
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assign cache_write_request = i_cache_req && i_write_enable;
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assign cache_write_request = i_cache_req && i_write_enable;
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assign start_access = core_read_request || core_write_request || i_cache_req ;
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assign wb_wait = o_wb_stb && !i_wb_ack;
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assign start_access = (core_read_request || core_write_request || i_cache_req) && !wb_wait ;
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// For writes the byte enable is always 4'hf
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// For writes the byte enable is always 4'hf
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assign byte_enable = ( core_write_request || cache_write_request ) ? i_byte_enable : 4'hf;
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assign byte_enable = wbuf_busy_r ? wbuf_sel_r :
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( core_write_request || cache_write_request ) ? i_byte_enable :
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4'hf ;
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// ======================================
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// Write buffer
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// ======================================
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always @( posedge i_clk )
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if ( wb_wait && !wbuf_busy_r && (core_write_request || cache_write_request) )
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begin
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wbuf_data_r <= i_write_data;
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wbuf_addr_r <= i_address;
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wbuf_sel_r <= i_byte_enable;
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wbuf_busy_r <= 1'd1;
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end
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else if (!o_wb_stb)
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wbuf_busy_r <= 1'd0;
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// ======================================
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// ======================================
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// Register Accesses
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// Register Accesses
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// ======================================
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// ======================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( start_access )
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if ( start_access )
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| Line 185... |
Line 214... |
exclusive_access <= i_exclusive;
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exclusive_access <= i_exclusive;
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if ( start_access )
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if ( start_access )
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begin
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begin
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if (wbuf_busy_r)
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begin
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o_wb_we <= 1'd1;
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o_wb_adr[31:2] <= wbuf_addr_r[31:2];
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end
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else
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begin
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o_wb_we <= core_write_request || cache_write_request;
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o_wb_we <= core_write_request || cache_write_request;
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// only update these on new wb access to make debug easier
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// only update these on new wb access to make debug easier
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o_wb_adr[31:2] <= i_address[31:2];
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o_wb_adr[31:2] <= i_address[31:2];
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end
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o_wb_adr[1:0] <= byte_enable == 4'b0001 ? 2'd0 :
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o_wb_adr[1:0] <= byte_enable == 4'b0001 ? 2'd0 :
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byte_enable == 4'b0010 ? 2'd1 :
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byte_enable == 4'b0010 ? 2'd1 :
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byte_enable == 4'b0100 ? 2'd2 :
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byte_enable == 4'b0100 ? 2'd2 :
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byte_enable == 4'b1000 ? 2'd3 :
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byte_enable == 4'b1000 ? 2'd3 :
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