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[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] [a23_wishbone.v] - Diff between revs 42 and 53

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Rev 42 Rev 53
Line 105... Line 105...
wire                        read_ack;
wire                        read_ack;
wire                        wait_write_ack;
wire                        wait_write_ack;
wire                        wb_wait;
wire                        wb_wait;
 
 
// Write buffer
// Write buffer
reg     [31:0]              wbuf_data_r = 'd0;
 
reg     [31:0]              wbuf_addr_r = 'd0;
reg     [31:0]              wbuf_addr_r = 'd0;
reg     [3:0]               wbuf_sel_r  = 'd0;
reg     [3:0]               wbuf_sel_r  = 'd0;
reg                         wbuf_busy_r = 'd0;
reg                         wbuf_busy_r = 'd0;
 
 
 
 
Line 147... Line 146...
 
 
 
 
always @( posedge i_clk )
always @( posedge i_clk )
    if ( wb_wait && !wbuf_busy_r && (core_write_request || cache_write_request) )
    if ( wb_wait && !wbuf_busy_r && (core_write_request || cache_write_request) )
        begin
        begin
        wbuf_data_r <= i_write_data;
 
        wbuf_addr_r <= i_address;
        wbuf_addr_r <= i_address;
        wbuf_sel_r  <= i_byte_enable;
        wbuf_sel_r  <= i_byte_enable;
        wbuf_busy_r <= 1'd1;
        wbuf_busy_r <= 1'd1;
        end
        end
    else if (!o_wb_stb)
    else if (!o_wb_stb)

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