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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_coprocessor.v] - Diff between revs 16 and 35

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Rev 16 Rev 35
Line 39... Line 39...
 
 
 
 
module a25_coprocessor
module a25_coprocessor
(
(
input                       i_clk,
input                       i_clk,
input                       i_access_stall,   // stall all stages of the cpu at the same time
input                       i_core_stall,     // stall all stages of the Amber core at the same time
input       [2:0]           i_copro_opcode1,
input       [2:0]           i_copro_opcode1,
input       [2:0]           i_copro_opcode2,
input       [2:0]           i_copro_opcode2,
input       [3:0]           i_copro_crn,      // Register Number 
input       [3:0]           i_copro_crn,      // Register Number 
input       [3:0]           i_copro_crm,
input       [3:0]           i_copro_crm,
input       [3:0]           i_copro_num,
input       [3:0]           i_copro_num,
Line 96... Line 96...
 
 
// ---------------------------
// ---------------------------
// Capture an access fault address and status
// Capture an access fault address and status
// ---------------------------
// ---------------------------
always @ ( posedge i_clk )
always @ ( posedge i_clk )
    if ( !i_access_stall )
    if ( !i_core_stall )
        begin
        begin
        if ( i_fault )
        if ( i_fault )
            begin
            begin
 
 
            `ifdef A25_COPRO15_DEBUG
            `ifdef A25_COPRO15_DEBUG
Line 115... Line 115...
 
 
// ---------------------------
// ---------------------------
// Register Writes
// Register Writes
// ---------------------------
// ---------------------------
always @ ( posedge i_clk )
always @ ( posedge i_clk )
    if ( !i_access_stall )
    if ( !i_core_stall )
        begin
        begin
        if ( i_copro_operation == 2'd2 )
        if ( i_copro_operation == 2'd2 )
            case ( i_copro_crn )
            case ( i_copro_crn )
                4'd2: cache_control   <= i_copro_write_data[2:0];
                4'd2: cache_control   <= i_copro_write_data[2:0];
                4'd3: cacheable_area  <= i_copro_write_data[31:0];
                4'd3: cacheable_area  <= i_copro_write_data[31:0];
Line 127... Line 127...
                4'd5: disruptive_area <= i_copro_write_data[31:0];
                4'd5: disruptive_area <= i_copro_write_data[31:0];
            endcase
            endcase
        end
        end
 
 
// Flush the cache
// Flush the cache
assign copro15_reg1_write = !i_access_stall && i_copro_operation == 2'd2 && i_copro_crn == 4'd1;
assign copro15_reg1_write = !i_core_stall && i_copro_operation == 2'd2 && i_copro_crn == 4'd1;
 
 
 
 
// ---------------------------
// ---------------------------
// Register Reads   
// Register Reads   
// ---------------------------
// ---------------------------
always @ ( posedge i_clk )
always @ ( posedge i_clk )
    if ( !i_access_stall )
    if ( !i_core_stall )
        case ( i_copro_crn )
        case ( i_copro_crn )
            // ID Register - [31:24] Company id, [23:16] Manuf id, [15:8] Part type, [7:0] revision
            // ID Register - [31:24] Company id, [23:16] Manuf id, [15:8] Part type, [7:0] revision
            4'd0:    o_copro_read_data <= 32'h4156_0300;
            4'd0:    o_copro_read_data <= 32'h4156_0300;
            4'd2:    o_copro_read_data <= {29'd0, cache_control};
            4'd2:    o_copro_read_data <= {29'd0, cache_control};
            4'd3:    o_copro_read_data <= cacheable_area;
            4'd3:    o_copro_read_data <= cacheable_area;
Line 159... Line 159...
//synopsys translate_off
//synopsys translate_off
reg [1:0]  copro_operation_d1;
reg [1:0]  copro_operation_d1;
reg [3:0]  copro_crn_d1;
reg [3:0]  copro_crn_d1;
 
 
always @( posedge i_clk )
always @( posedge i_clk )
    if ( !i_access_stall )
    if ( !i_core_stall )
        begin
        begin
        copro_operation_d1  <= i_copro_operation;
        copro_operation_d1  <= i_copro_operation;
        copro_crn_d1        <= i_copro_crn;
        copro_crn_d1        <= i_copro_crn;
        end
        end
 
 
always @( posedge i_clk )
always @( posedge i_clk )
    if ( !i_access_stall )
    if ( !i_core_stall )
        begin
        begin
        if ( i_copro_operation == 2'd2 )  // mcr
        if ( i_copro_operation == 2'd2 )  // mcr
            case ( i_copro_crn )
            case ( i_copro_crn )
                4'd 1: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #1, Flush Cache", i_copro_write_data); end
                4'd 1: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #1, Flush Cache", i_copro_write_data); end
                4'd 2: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #2, Cache Control", i_copro_write_data); end
                4'd 2: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #2, Cache Control", i_copro_write_data); end

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