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module a25_coprocessor
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module a25_coprocessor
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(
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(
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input i_clk,
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input i_clk,
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input i_access_stall, // stall all stages of the cpu at the same time
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input i_core_stall, // stall all stages of the Amber core at the same time
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input [2:0] i_copro_opcode1,
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input [2:0] i_copro_opcode1,
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input [2:0] i_copro_opcode2,
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input [2:0] i_copro_opcode2,
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input [3:0] i_copro_crn, // Register Number
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input [3:0] i_copro_crn, // Register Number
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input [3:0] i_copro_crm,
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input [3:0] i_copro_crm,
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input [3:0] i_copro_num,
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input [3:0] i_copro_num,
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// ---------------------------
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// ---------------------------
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// Capture an access fault address and status
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// Capture an access fault address and status
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// ---------------------------
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// ---------------------------
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always @ ( posedge i_clk )
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always @ ( posedge i_clk )
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if ( !i_access_stall )
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if ( !i_core_stall )
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begin
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begin
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if ( i_fault )
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if ( i_fault )
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begin
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begin
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`ifdef A25_COPRO15_DEBUG
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`ifdef A25_COPRO15_DEBUG
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// ---------------------------
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// ---------------------------
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// Register Writes
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// Register Writes
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// ---------------------------
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// ---------------------------
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always @ ( posedge i_clk )
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always @ ( posedge i_clk )
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if ( !i_access_stall )
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if ( !i_core_stall )
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begin
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begin
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if ( i_copro_operation == 2'd2 )
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if ( i_copro_operation == 2'd2 )
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case ( i_copro_crn )
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case ( i_copro_crn )
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4'd2: cache_control <= i_copro_write_data[2:0];
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4'd2: cache_control <= i_copro_write_data[2:0];
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4'd3: cacheable_area <= i_copro_write_data[31:0];
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4'd3: cacheable_area <= i_copro_write_data[31:0];
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4'd5: disruptive_area <= i_copro_write_data[31:0];
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4'd5: disruptive_area <= i_copro_write_data[31:0];
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endcase
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endcase
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end
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end
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// Flush the cache
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// Flush the cache
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assign copro15_reg1_write = !i_access_stall && i_copro_operation == 2'd2 && i_copro_crn == 4'd1;
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assign copro15_reg1_write = !i_core_stall && i_copro_operation == 2'd2 && i_copro_crn == 4'd1;
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// ---------------------------
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// ---------------------------
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// Register Reads
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// Register Reads
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// ---------------------------
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// ---------------------------
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always @ ( posedge i_clk )
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always @ ( posedge i_clk )
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if ( !i_access_stall )
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if ( !i_core_stall )
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case ( i_copro_crn )
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case ( i_copro_crn )
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// ID Register - [31:24] Company id, [23:16] Manuf id, [15:8] Part type, [7:0] revision
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// ID Register - [31:24] Company id, [23:16] Manuf id, [15:8] Part type, [7:0] revision
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4'd0: o_copro_read_data <= 32'h4156_0300;
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4'd0: o_copro_read_data <= 32'h4156_0300;
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4'd2: o_copro_read_data <= {29'd0, cache_control};
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4'd2: o_copro_read_data <= {29'd0, cache_control};
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4'd3: o_copro_read_data <= cacheable_area;
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4'd3: o_copro_read_data <= cacheable_area;
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//synopsys translate_off
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//synopsys translate_off
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reg [1:0] copro_operation_d1;
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reg [1:0] copro_operation_d1;
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reg [3:0] copro_crn_d1;
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reg [3:0] copro_crn_d1;
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( !i_access_stall )
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if ( !i_core_stall )
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begin
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begin
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copro_operation_d1 <= i_copro_operation;
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copro_operation_d1 <= i_copro_operation;
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copro_crn_d1 <= i_copro_crn;
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copro_crn_d1 <= i_copro_crn;
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end
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end
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( !i_access_stall )
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if ( !i_core_stall )
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begin
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begin
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if ( i_copro_operation == 2'd2 ) // mcr
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if ( i_copro_operation == 2'd2 ) // mcr
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case ( i_copro_crn )
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case ( i_copro_crn )
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4'd 1: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to Co-Pro 15 #1, Flush Cache", i_copro_write_data); end
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4'd 1: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to Co-Pro 15 #1, Flush Cache", i_copro_write_data); end
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4'd 2: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to Co-Pro 15 #2, Cache Control", i_copro_write_data); end
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4'd 2: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to Co-Pro 15 #2, Cache Control", i_copro_write_data); end
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