| Line 176... |
Line 176... |
wire [31:0] icache_wb_adr;
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wire [31:0] icache_wb_adr;
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wire [31:0] icache_wb_read_data;
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wire [31:0] icache_wb_read_data;
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wire icache_wb_ready;
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wire icache_wb_ready;
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wire conflict;
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wire conflict;
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wire rn_use_read;
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wire rm_use_read;
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wire rs_use_read;
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wire rd_use_read;
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// data abort has priority
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// data abort has priority
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assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status;
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assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status;
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assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
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assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
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assign decode_fault = dabt_trigger | iabt_trigger;
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assign decode_fault = dabt_trigger | iabt_trigger;
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| Line 285... |
Line 288... |
.o_iabt_status ( iabt_fault_status ),
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.o_iabt_status ( iabt_fault_status ),
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.o_dabt_trigger ( dabt_trigger ),
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.o_dabt_trigger ( dabt_trigger ),
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.o_dabt_address ( dabt_fault_address ),
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.o_dabt_address ( dabt_fault_address ),
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.o_dabt_status ( dabt_fault_status ),
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.o_dabt_status ( dabt_fault_status ),
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.o_conflict ( conflict )
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.o_conflict ( conflict ),
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.o_rn_use_read ( rn_use_read ),
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.o_rm_use_read ( rm_use_read ),
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.o_rs_use_read ( rs_use_read ),
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.o_rd_use_read ( rd_use_read )
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);
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);
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// ======================================
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// ======================================
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// Execute Stage
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// Execute Stage
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| Line 358... |
Line 365... |
.i_status_bits_flags_wen ( status_bits_flags_wen ),
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.i_status_bits_flags_wen ( status_bits_flags_wen ),
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.i_status_bits_mode_wen ( status_bits_mode_wen ),
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.i_status_bits_mode_wen ( status_bits_mode_wen ),
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.i_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
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.i_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
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.i_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
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.i_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
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.i_copro_write_data_wen ( copro_write_data_wen ),
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.i_copro_write_data_wen ( copro_write_data_wen ),
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.i_conflict ( conflict )
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.i_conflict ( conflict ),
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.i_rn_use_read ( rn_use_read ),
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.i_rm_use_read ( rm_use_read ),
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.i_rs_use_read ( rs_use_read ),
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.i_rd_use_read ( rd_use_read )
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);
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);
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// ======================================
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// ======================================
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// Memory access stage with data cache
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// Memory access stage with data cache
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