| Line 51... |
Line 51... |
|
|
input i_system_rdy, // Amber is stalled when this is low
|
input i_system_rdy, // Amber is stalled when this is low
|
|
|
// Wishbone Master I/F
|
// Wishbone Master I/F
|
output [31:0] o_wb_adr,
|
output [31:0] o_wb_adr,
|
output [3:0] o_wb_sel,
|
output [15:0] o_wb_sel,
|
output o_wb_we,
|
output o_wb_we,
|
input [31:0] i_wb_dat,
|
input [127:0] i_wb_dat,
|
output [31:0] o_wb_dat,
|
output [127:0] o_wb_dat,
|
output o_wb_cyc,
|
output o_wb_cyc,
|
output o_wb_stb,
|
output o_wb_stb,
|
input i_wb_ack,
|
input i_wb_ack,
|
input i_wb_err
|
input i_wb_err
|
|
|
| Line 84... |
Line 84... |
wire cache_flush; // Flush the cache
|
wire cache_flush; // Flush the cache
|
wire [31:0] cacheable_area;
|
wire [31:0] cacheable_area;
|
|
|
wire fetch_stall;
|
wire fetch_stall;
|
wire mem_stall;
|
wire mem_stall;
|
wire access_stall;
|
wire exec_stall;
|
|
wire core_stall;
|
|
|
wire [1:0] status_bits_mode;
|
wire [1:0] status_bits_mode;
|
wire status_bits_irq_mask;
|
wire status_bits_irq_mask;
|
wire status_bits_firq_mask;
|
wire status_bits_firq_mask;
|
wire status_bits_flags_wen;
|
wire status_bits_flags_wen;
|
| Line 103... |
Line 104... |
wire [3:0] condition;
|
wire [3:0] condition;
|
|
|
wire [3:0] rm_sel;
|
wire [3:0] rm_sel;
|
wire [3:0] rs_sel;
|
wire [3:0] rs_sel;
|
wire [7:0] decode_load_rd;
|
wire [7:0] decode_load_rd;
|
wire [7:0] exec_load_rd;
|
wire [8:0] exec_load_rd;
|
wire [3:0] rn_sel;
|
wire [3:0] rn_sel;
|
wire [1:0] barrel_shift_amount_sel;
|
wire [1:0] barrel_shift_amount_sel;
|
wire [1:0] barrel_shift_data_sel;
|
wire [1:0] barrel_shift_data_sel;
|
wire [1:0] barrel_shift_function;
|
wire [1:0] barrel_shift_function;
|
wire [8:0] alu_function;
|
wire [8:0] alu_function;
|
| Line 152... |
Line 153... |
|
|
wire adex;
|
wire adex;
|
|
|
wire [31:0] mem_read_data;
|
wire [31:0] mem_read_data;
|
wire mem_read_data_valid;
|
wire mem_read_data_valid;
|
wire [9:0] mem_load_rd;
|
wire [10:0] mem_load_rd;
|
|
|
wire [31:0] wb_read_data;
|
wire [31:0] wb_read_data;
|
wire wb_read_data_valid;
|
wire wb_read_data_valid;
|
wire [9:0] wb_load_rd;
|
wire [10:0] wb_load_rd;
|
|
|
wire dcache_wb_cached_req;
|
wire dcache_wb_cached_req;
|
wire dcache_wb_uncached_req;
|
wire dcache_wb_uncached_req;
|
wire dcache_wb_qword;
|
wire dcache_wb_qword;
|
wire dcache_wb_write;
|
wire dcache_wb_write;
|
wire [3:0] dcache_wb_byte_enable;
|
wire [15:0] dcache_wb_byte_enable;
|
wire [31:0] dcache_wb_address;
|
wire [31:0] dcache_wb_address;
|
wire [31:0] dcache_wb_read_data;
|
wire [127:0] dcache_wb_cached_rdata;
|
wire [31:0] dcache_wb_write_data;
|
wire [127:0] dcache_wb_uncached_rdata;
|
|
wire [127:0] dcache_wb_write_data;
|
wire dcache_wb_cached_ready;
|
wire dcache_wb_cached_ready;
|
wire dcache_wb_uncached_ready;
|
wire dcache_wb_uncached_ready;
|
wire [31:0] icache_wb_address;
|
wire [31:0] icache_wb_address;
|
wire icache_wb_req;
|
wire icache_wb_req;
|
wire icache_wb_qword;
|
|
wire [31:0] icache_wb_adr;
|
wire [31:0] icache_wb_adr;
|
wire [31:0] icache_wb_read_data;
|
wire [127:0] icache_wb_read_data;
|
wire icache_wb_ready;
|
wire icache_wb_ready;
|
|
|
wire conflict;
|
wire conflict;
|
wire rn_use_read;
|
wire rn_use_read;
|
wire rm_use_read;
|
wire rm_use_read;
|
| Line 186... |
Line 187... |
// data abort has priority
|
// data abort has priority
|
assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status;
|
assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status;
|
assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
|
assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
|
assign decode_fault = dabt_trigger | iabt_trigger;
|
assign decode_fault = dabt_trigger | iabt_trigger;
|
|
|
assign access_stall = fetch_stall || mem_stall;
|
assign core_stall = fetch_stall || mem_stall || exec_stall;
|
|
|
// ======================================
|
// ======================================
|
// Fetch Stage
|
// Fetch Stage
|
// ======================================
|
// ======================================
|
a25_fetch u_fetch (
|
a25_fetch u_fetch (
|
.i_clk ( i_clk ),
|
.i_clk ( i_clk ),
|
.i_mem_stall ( mem_stall ),
|
.i_mem_stall ( mem_stall ),
|
|
.i_exec_stall ( exec_stall ),
|
.i_conflict ( conflict ),
|
.i_conflict ( conflict ),
|
.i_system_rdy ( i_system_rdy ),
|
.i_system_rdy ( i_system_rdy ),
|
.o_fetch_stall ( fetch_stall ),
|
.o_fetch_stall ( fetch_stall ),
|
|
|
.i_iaddress ( {execute_iaddress[31:2], 2'd0} ),
|
.i_iaddress ( {execute_iaddress[31:2], 2'd0} ),
|
| Line 206... |
Line 208... |
.o_fetch_instruction ( fetch_instruction ),
|
.o_fetch_instruction ( fetch_instruction ),
|
.i_cache_enable ( cache_enable ),
|
.i_cache_enable ( cache_enable ),
|
.i_cache_flush ( cache_flush ),
|
.i_cache_flush ( cache_flush ),
|
.i_cacheable_area ( cacheable_area ),
|
.i_cacheable_area ( cacheable_area ),
|
|
|
|
|
.o_wb_req ( icache_wb_req ),
|
.o_wb_req ( icache_wb_req ),
|
.o_wb_qword ( icache_wb_qword ),
|
|
.o_wb_address ( icache_wb_address ),
|
.o_wb_address ( icache_wb_address ),
|
.i_wb_read_data ( icache_wb_read_data ),
|
.i_wb_read_data ( icache_wb_read_data ),
|
.i_wb_ready ( icache_wb_ready )
|
.i_wb_ready ( icache_wb_ready )
|
);
|
);
|
|
|
| Line 220... |
Line 220... |
// ======================================
|
// ======================================
|
// Decode Stage
|
// Decode Stage
|
// ======================================
|
// ======================================
|
a25_decode u_decode (
|
a25_decode u_decode (
|
.i_clk ( i_clk ),
|
.i_clk ( i_clk ),
|
.i_access_stall ( access_stall ),
|
.i_core_stall ( core_stall ),
|
|
|
// Instruction fetch or data read signals
|
// Instruction fetch or data read signals
|
.i_fetch_instruction ( fetch_instruction ),
|
.i_fetch_instruction ( fetch_instruction ),
|
.i_execute_iaddress ( execute_iaddress ),
|
.i_execute_iaddress ( execute_iaddress ),
|
.i_execute_daddress ( execute_daddress ),
|
.i_execute_daddress ( execute_daddress ),
|
| Line 301... |
Line 301... |
// ======================================
|
// ======================================
|
// Execute Stage
|
// Execute Stage
|
// ======================================
|
// ======================================
|
a25_execute u_execute (
|
a25_execute u_execute (
|
.i_clk ( i_clk ),
|
.i_clk ( i_clk ),
|
.i_access_stall ( access_stall ),
|
.i_core_stall ( core_stall ),
|
.i_mem_stall ( mem_stall ),
|
.i_mem_stall ( mem_stall ),
|
|
.o_exec_stall ( exec_stall ),
|
|
|
.i_wb_read_data ( wb_read_data ),
|
.i_wb_read_data ( wb_read_data ),
|
.i_wb_read_data_valid ( wb_read_data_valid ),
|
.i_wb_read_data_valid ( wb_read_data_valid ),
|
.i_wb_load_rd ( wb_load_rd ),
|
.i_wb_load_rd ( wb_load_rd ),
|
|
|
| Line 379... |
Line 380... |
// Memory access stage with data cache
|
// Memory access stage with data cache
|
// ======================================
|
// ======================================
|
a25_mem u_mem (
|
a25_mem u_mem (
|
.i_clk ( i_clk ),
|
.i_clk ( i_clk ),
|
.i_fetch_stall ( fetch_stall ),
|
.i_fetch_stall ( fetch_stall ),
|
|
.i_exec_stall ( exec_stall ),
|
.o_mem_stall ( mem_stall ),
|
.o_mem_stall ( mem_stall ),
|
|
|
.i_daddress ( execute_daddress ),
|
.i_daddress ( execute_daddress ),
|
.i_daddress_valid ( execute_daddress_valid ),
|
.i_daddress_valid ( execute_daddress_valid ),
|
.i_daddress_nxt ( execute_daddress_nxt ),
|
.i_daddress_nxt ( execute_daddress_nxt ),
|
| Line 405... |
Line 407... |
.o_wb_qword ( dcache_wb_qword ),
|
.o_wb_qword ( dcache_wb_qword ),
|
.o_wb_write ( dcache_wb_write ),
|
.o_wb_write ( dcache_wb_write ),
|
.o_wb_write_data ( dcache_wb_write_data ),
|
.o_wb_write_data ( dcache_wb_write_data ),
|
.o_wb_byte_enable ( dcache_wb_byte_enable ),
|
.o_wb_byte_enable ( dcache_wb_byte_enable ),
|
.o_wb_address ( dcache_wb_address ),
|
.o_wb_address ( dcache_wb_address ),
|
.i_wb_read_data ( dcache_wb_read_data ),
|
|
.i_wb_cached_ready ( dcache_wb_cached_ready ),
|
.i_wb_cached_ready ( dcache_wb_cached_ready ),
|
.i_wb_uncached_ready ( dcache_wb_uncached_ready )
|
.i_wb_cached_rdata ( dcache_wb_cached_rdata ),
|
|
.i_wb_uncached_ready ( dcache_wb_uncached_ready ),
|
|
.i_wb_uncached_rdata ( dcache_wb_cached_rdata )
|
);
|
);
|
|
|
|
|
// ======================================
|
// ======================================
|
// Write back stage with data cache
|
// Write back stage with data cache
|
| Line 432... |
Line 435... |
.o_wb_load_rd ( wb_load_rd )
|
.o_wb_load_rd ( wb_load_rd )
|
);
|
);
|
|
|
|
|
|
|
|
|
// ======================================
|
// ======================================
|
// Wishbone Master I/F
|
// Wishbone Master I/F
|
// ======================================
|
// ======================================
|
a25_wishbone u_wishbone (
|
a25_wishbone u_wishbone (
|
// CPU Side
|
// CPU Side
|
.i_clk ( i_clk ),
|
.i_clk ( i_clk ),
|
|
|
// Instruction Cache Accesses
|
// Port 0 - dcache uncached
|
.i_icache_req ( icache_wb_req ),
|
.i_port0_req ( dcache_wb_uncached_req ),
|
.i_icache_qword ( icache_wb_qword ),
|
.i_port0_write ( dcache_wb_write ),
|
.i_icache_address ( icache_wb_address ),
|
.i_port0_wdata ( dcache_wb_write_data ),
|
.o_icache_read_data ( icache_wb_read_data ),
|
.i_port0_be ( dcache_wb_byte_enable ),
|
.o_icache_ready ( icache_wb_ready ),
|
.i_port0_addr ( dcache_wb_address ),
|
|
.o_port0_rdata ( dcache_wb_uncached_rdata ),
|
// Data Cache Accesses
|
.o_port0_ready ( dcache_wb_uncached_ready ),
|
.i_exclusive ( exclusive ),
|
|
.i_dcache_cached_req ( dcache_wb_cached_req ),
|
// Port 1 - dcache cached
|
.i_dcache_uncached_req ( dcache_wb_uncached_req ),
|
.i_port1_req ( dcache_wb_cached_req ),
|
.i_dcache_qword ( dcache_wb_qword ),
|
.i_port1_write ( dcache_wb_write ),
|
.i_dcache_write ( dcache_wb_write ),
|
.i_port1_wdata ( dcache_wb_write_data ),
|
.i_dcache_write_data ( dcache_wb_write_data ),
|
.i_port1_be ( dcache_wb_byte_enable ),
|
.i_dcache_byte_enable ( dcache_wb_byte_enable ),
|
.i_port1_addr ( dcache_wb_address ),
|
.i_dcache_address ( dcache_wb_address ),
|
.o_port1_rdata ( dcache_wb_cached_rdata ),
|
.o_dcache_read_data ( dcache_wb_read_data ),
|
.o_port1_ready ( dcache_wb_cached_ready ),
|
.o_dcache_cached_ready ( dcache_wb_cached_ready ),
|
|
.o_dcache_uncached_ready ( dcache_wb_uncached_ready ),
|
// Port 2 - instruction cache accesses, read only
|
|
.i_port2_req ( icache_wb_req ),
|
|
.i_port2_write ( 1'd0 ),
|
|
.i_port2_wdata ( 128'd0 ),
|
|
.i_port2_be ( 16'd0 ),
|
|
.i_port2_addr ( icache_wb_address ),
|
|
.o_port2_rdata ( icache_wb_read_data ),
|
|
.o_port2_ready ( icache_wb_ready ),
|
|
|
|
// Wishbone
|
.o_wb_adr ( o_wb_adr ),
|
.o_wb_adr ( o_wb_adr ),
|
.o_wb_sel ( o_wb_sel ),
|
.o_wb_sel ( o_wb_sel ),
|
.o_wb_we ( o_wb_we ),
|
.o_wb_we ( o_wb_we ),
|
.i_wb_dat ( i_wb_dat ),
|
.i_wb_dat ( i_wb_dat ),
|
.o_wb_dat ( o_wb_dat ),
|
.o_wb_dat ( o_wb_dat ),
|
| Line 471... |
Line 483... |
.i_wb_ack ( i_wb_ack ),
|
.i_wb_ack ( i_wb_ack ),
|
.i_wb_err ( i_wb_err )
|
.i_wb_err ( i_wb_err )
|
);
|
);
|
|
|
|
|
|
|
// ======================================
|
// ======================================
|
// Co-Processor #15
|
// Co-Processor #15
|
// ======================================
|
// ======================================
|
a25_coprocessor u_coprocessor (
|
a25_coprocessor u_coprocessor (
|
.i_clk ( i_clk ),
|
.i_clk ( i_clk ),
|
.i_access_stall ( access_stall ),
|
.i_core_stall ( core_stall ),
|
|
|
.i_copro_opcode1 ( copro_opcode1 ),
|
.i_copro_opcode1 ( copro_opcode1 ),
|
.i_copro_opcode2 ( copro_opcode2 ),
|
.i_copro_opcode2 ( copro_opcode2 ),
|
.i_copro_crn ( copro_crn ),
|
.i_copro_crn ( copro_crn ),
|
.i_copro_crm ( copro_crm ),
|
.i_copro_crm ( copro_crm ),
|
