| Line 161... |
Line 161... |
wire wb_read_data_valid;
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wire wb_read_data_valid;
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wire [10:0] wb_load_rd;
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wire [10:0] wb_load_rd;
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wire dcache_wb_cached_req;
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wire dcache_wb_cached_req;
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wire dcache_wb_uncached_req;
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wire dcache_wb_uncached_req;
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wire dcache_wb_qword;
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wire dcache_wb_write;
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wire dcache_wb_write;
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wire [15:0] dcache_wb_byte_enable;
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wire [15:0] dcache_wb_byte_enable;
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wire [31:0] dcache_wb_address;
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wire [31:0] dcache_wb_address;
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wire [127:0] dcache_wb_cached_rdata;
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wire [127:0] dcache_wb_cached_rdata;
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wire [127:0] dcache_wb_uncached_rdata;
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wire [127:0] dcache_wb_uncached_rdata;
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| Line 402... |
Line 401... |
.i_cache_flush ( cache_flush ),
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.i_cache_flush ( cache_flush ),
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.i_cacheable_area ( cacheable_area ),
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.i_cacheable_area ( cacheable_area ),
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.o_wb_cached_req ( dcache_wb_cached_req ),
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.o_wb_cached_req ( dcache_wb_cached_req ),
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.o_wb_uncached_req ( dcache_wb_uncached_req ),
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.o_wb_uncached_req ( dcache_wb_uncached_req ),
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.o_wb_qword ( dcache_wb_qword ),
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.o_wb_write ( dcache_wb_write ),
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.o_wb_write ( dcache_wb_write ),
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.o_wb_write_data ( dcache_wb_write_data ),
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.o_wb_write_data ( dcache_wb_write_data ),
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.o_wb_byte_enable ( dcache_wb_byte_enable ),
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.o_wb_byte_enable ( dcache_wb_byte_enable ),
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.o_wb_address ( dcache_wb_address ),
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.o_wb_address ( dcache_wb_address ),
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.i_wb_cached_ready ( dcache_wb_cached_ready ),
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.i_wb_cached_ready ( dcache_wb_cached_ready ),
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| Line 445... |
Line 443... |
// CPU Side
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// CPU Side
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.i_clk ( i_clk ),
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.i_clk ( i_clk ),
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// Port 0 - dcache uncached
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// Port 0 - dcache uncached
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.i_port0_req ( dcache_wb_uncached_req ),
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.i_port0_req ( dcache_wb_uncached_req ),
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.o_port0_ack ( dcache_wb_uncached_ready ),
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.i_port0_write ( dcache_wb_write ),
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.i_port0_write ( dcache_wb_write ),
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.i_port0_wdata ( dcache_wb_write_data ),
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.i_port0_wdata ( dcache_wb_write_data ),
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.i_port0_be ( dcache_wb_byte_enable ),
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.i_port0_be ( dcache_wb_byte_enable ),
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.i_port0_addr ( dcache_wb_address ),
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.i_port0_addr ( dcache_wb_address ),
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.o_port0_rdata ( dcache_wb_uncached_rdata ),
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.o_port0_rdata ( dcache_wb_uncached_rdata ),
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.o_port0_ready ( dcache_wb_uncached_ready ),
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// Port 1 - dcache cached
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// Port 1 - dcache cached
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.i_port1_req ( dcache_wb_cached_req ),
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.i_port1_req ( dcache_wb_cached_req ),
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.o_port1_ack ( dcache_wb_cached_ready ),
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.i_port1_write ( dcache_wb_write ),
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.i_port1_write ( dcache_wb_write ),
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.i_port1_wdata ( dcache_wb_write_data ),
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.i_port1_wdata ( dcache_wb_write_data ),
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.i_port1_be ( dcache_wb_byte_enable ),
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.i_port1_be ( dcache_wb_byte_enable ),
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.i_port1_addr ( dcache_wb_address ),
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.i_port1_addr ( dcache_wb_address ),
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.o_port1_rdata ( dcache_wb_cached_rdata ),
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.o_port1_rdata ( dcache_wb_cached_rdata ),
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.o_port1_ready ( dcache_wb_cached_ready ),
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// Port 2 - instruction cache accesses, read only
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// Port 2 - instruction cache accesses, read only
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.i_port2_req ( icache_wb_req ),
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.i_port2_req ( icache_wb_req ),
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.o_port2_ack ( icache_wb_ready ),
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.i_port2_write ( 1'd0 ),
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.i_port2_write ( 1'd0 ),
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.i_port2_wdata ( 128'd0 ),
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.i_port2_wdata ( 128'd0 ),
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.i_port2_be ( 16'd0 ),
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.i_port2_be ( 16'd0 ),
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.i_port2_addr ( icache_wb_address ),
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.i_port2_addr ( icache_wb_address ),
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.o_port2_rdata ( icache_wb_read_data ),
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.o_port2_rdata ( icache_wb_read_data ),
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.o_port2_ready ( icache_wb_ready ),
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// Wishbone
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// Wishbone
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.o_wb_adr ( o_wb_adr ),
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.o_wb_adr ( o_wb_adr ),
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.o_wb_sel ( o_wb_sel ),
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.o_wb_sel ( o_wb_sel ),
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.o_wb_we ( o_wb_we ),
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.o_wb_we ( o_wb_we ),
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