| Line 115... |
Line 115... |
C_INVA = 3,
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C_INVA = 3,
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C_STATES = 4;
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C_STATES = 4;
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localparam [3:0] CS_INIT = 4'd0,
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localparam [3:0] CS_INIT = 4'd0,
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CS_IDLE = 4'd1,
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CS_IDLE = 4'd1,
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CS_FILL0 = 4'd2,
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CS_FILL = 4'd2,
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CS_FILL1 = 4'd3,
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CS_FILL_COMPLETE = 4'd3,
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CS_FILL2 = 4'd4,
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CS_TURN_AROUND = 4'd4,
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CS_FILL3 = 4'd5,
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CS_WRITE_HIT = 4'd5,
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CS_FILL_COMPLETE = 4'd6,
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CS_WRITE_HIT_WAIT_WB = 4'd6,
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CS_TURN_AROUND = 4'd7,
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CS_WRITE_MISS_WAIT_WB = 4'd7,
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CS_WRITE_HIT1 = 4'd8,
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CS_EX_DELETE = 4'd8;
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CS_WRITE_HIT_WAIT_WB = 4'd8,
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CS_WRITE_MISS_WAIT_WB = 4'd9,
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CS_EX_DELETE = 4'd10;
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reg [3:0] c_state = CS_IDLE;
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reg [3:0] c_state = CS_IDLE;
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reg [C_STATES-1:0] source_sel = 1'd1 << C_CORE;
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reg [C_STATES-1:0] source_sel = 1'd1 << C_CORE;
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reg [CACHE_ADDR_WIDTH:0] init_count = 'd0;
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reg [CACHE_ADDR_WIDTH:0] init_count = 'd0;
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| Line 264... |
Line 261... |
select_way <= data_hit_way | ex_read_hit_way;
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select_way <= data_hit_way | ex_read_hit_way;
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c_state <= CS_EX_DELETE;
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c_state <= CS_EX_DELETE;
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source_sel <= 1'd1 << C_INVA;
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source_sel <= 1'd1 << C_INVA;
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end
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end
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else if ( read_miss )
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else if ( read_miss )
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c_state <= CS_FILL3;
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c_state <= CS_FILL;
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else if ( write_hit )
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else if ( write_hit )
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begin
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begin
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if ( i_wb_cached_ready )
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if ( i_wb_cached_ready )
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c_state <= CS_WRITE_HIT1;
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c_state <= CS_WRITE_HIT;
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else
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else
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c_state <= CS_WRITE_HIT_WAIT_WB;
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c_state <= CS_WRITE_HIT_WAIT_WB;
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end
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end
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else if ( write_miss && !i_wb_cached_ready )
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else if ( write_miss && !i_wb_cached_ready )
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c_state <= CS_WRITE_MISS_WAIT_WB;
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c_state <= CS_WRITE_MISS_WAIT_WB;
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end
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end
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CS_FILL3 :
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CS_FILL :
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// third read of burst of 4
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// third read of burst of 4
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// wb read request asserted, wait for ack
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// wb read request asserted, wait for ack
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if ( i_wb_cached_ready )
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if ( i_wb_cached_ready )
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begin
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begin
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c_state <= CS_FILL_COMPLETE;
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c_state <= CS_FILL_COMPLETE;
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| Line 327... |
Line 324... |
c_state <= CS_TURN_AROUND;
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c_state <= CS_TURN_AROUND;
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source_sel <= 1'd1 << C_CORE;
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source_sel <= 1'd1 << C_CORE;
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end
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end
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CS_WRITE_HIT1:
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CS_WRITE_HIT:
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if ( !consecutive_write )
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if ( !consecutive_write )
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c_state <= CS_IDLE;
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c_state <= CS_IDLE;
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CS_WRITE_HIT_WAIT_WB:
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CS_WRITE_HIT_WAIT_WB:
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| Line 376... |
Line 373... |
data_wdata_r <= data_wdata;
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data_wdata_r <= data_wdata;
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end
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end
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assign consecutive_write = miss_address[31:4] == i_address[31:4] &&
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assign consecutive_write = miss_address[31:4] == i_address[31:4] &&
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i_write_enable &&
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i_write_enable &&
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c_state == CS_WRITE_HIT1 &&
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c_state == CS_WRITE_HIT &&
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request_pulse;
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request_pulse;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ( o_wb_cached_req )
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if ( o_wb_cached_req )
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wb_address <= i_address;
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wb_address <= i_address;
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else if ( i_wb_cached_ready && fill_state )
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else if ( i_wb_cached_ready && fill_state )
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wb_address <= {wb_address[31:4], wb_address[3:2] + 1'd1, 2'd0};
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wb_address <= {wb_address[31:4], wb_address[3:2] + 1'd1, 2'd0};
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assign fill_state = c_state == CS_FILL0 || c_state == CS_FILL1 || c_state == CS_FILL2 || c_state == CS_FILL3 ;
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assign fill_state = c_state == CS_FILL ;
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assign wb_hit = i_address == wb_address && i_wb_cached_ready && fill_state;
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assign wb_hit = i_address == wb_address && i_wb_cached_ready && fill_state;
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// ======================================
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// ======================================
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// Hold Requests
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// Hold Requests
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| Line 529... |
Line 526... |
assign ex_read_cache_busy = exclusive_access && !i_write_enable && c_state != CS_IDLE;
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assign ex_read_cache_busy = exclusive_access && !i_write_enable && c_state != CS_IDLE;
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// Need to stall for a write miss to wait for the current wb
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// Need to stall for a write miss to wait for the current wb
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// read miss access to complete. Also for a write idle_hit, need
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// read miss access to complete. Also for a write idle_hit, need
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// to stall for 1 cycle while the data cache is being written to
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// to stall for 1 cycle while the data cache is being written to
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assign write_state = c_state == CS_IDLE || c_state == CS_WRITE_HIT1 ||
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assign write_state = c_state == CS_IDLE || c_state == CS_WRITE_HIT ||
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c_state == CS_WRITE_HIT_WAIT_WB || c_state == CS_WRITE_MISS_WAIT_WB;
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c_state == CS_WRITE_HIT_WAIT_WB || c_state == CS_WRITE_MISS_WAIT_WB;
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assign write_stall = (write_miss && !(i_wb_cached_ready && write_state)) || (write_hit && !i_wb_cached_ready);
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assign write_stall = (write_miss && !(i_wb_cached_ready && write_state)) || (write_hit && !i_wb_cached_ready);
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assign read_stall = request_hold && !idle_hit && !rbuf_hit && !wb_hit && !i_write_enable;
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assign read_stall = request_hold && !idle_hit && !rbuf_hit && !wb_hit && !i_write_enable;
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assign cache_busy_stall = c_state == CS_FILL_COMPLETE || c_state == CS_TURN_AROUND || c_state == CS_INIT ||
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assign cache_busy_stall = c_state == CS_FILL_COMPLETE || c_state == CS_TURN_AROUND || c_state == CS_INIT ||
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(fill_state && !rbuf_hit && !wb_hit) ||
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(fill_state && !rbuf_hit && !wb_hit) ||
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(c_state == CS_WRITE_HIT1 && !consecutive_write);
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(c_state == CS_WRITE_HIT && !consecutive_write);
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// ======================================
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// ======================================
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// Instantiate RAMS
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// Instantiate RAMS
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// ======================================
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// ======================================
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| Line 870... |
Line 867... |
source_sel[C_INIT] ? "C_INIT" :
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source_sel[C_INIT] ? "C_INIT" :
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source_sel[C_FILL] ? "C_FILL" :
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source_sel[C_FILL] ? "C_FILL" :
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source_sel[C_INVA] ? "C_INVA" :
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source_sel[C_INVA] ? "C_INVA" :
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"UNKNON" ;
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"UNKNON" ;
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assign xC_STATE = c_state == CS_INIT ? "CS_INIT" :
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assign xC_STATE = c_state == CS_INIT ? "INIT" :
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c_state == CS_IDLE ? "CS_IDLE" :
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c_state == CS_IDLE ? "IDLE" :
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c_state == CS_FILL0 ? "CS_FILL0" :
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c_state == CS_FILL ? "FILL" :
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c_state == CS_FILL1 ? "CS_FILL1" :
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c_state == CS_FILL_COMPLETE ? "FILL_COMPLETE" :
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c_state == CS_FILL2 ? "CS_FILL2" :
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c_state == CS_EX_DELETE ? "EX_DELETE" :
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c_state == CS_FILL3 ? "CS_FILL3" :
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c_state == CS_TURN_AROUND ? "TURN_AROUND" :
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c_state == CS_FILL_COMPLETE ? "CS_FILL_COMPLETE" :
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c_state == CS_WRITE_HIT ? "WRITE_HIT" :
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c_state == CS_EX_DELETE ? "CS_EX_DELETE" :
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c_state == CS_WRITE_HIT_WAIT_WB ? "WRITE_HIT_WAIT_WB" :
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c_state == CS_TURN_AROUND ? "CS_TURN_AROUND" :
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c_state == CS_WRITE_MISS_WAIT_WB ? "WRITE_MISS_WAIT_WB" :
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c_state == CS_WRITE_HIT1 ? "CS_WRITE_HIT1" :
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c_state == CS_WRITE_HIT_WAIT_WB ? "CS_WRITE_HIT_WAIT_WB" :
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c_state == CS_WRITE_MISS_WAIT_WB ? "CS_WRITE_MISS_WAIT_WB" :
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"UNKNOWN" ;
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"UNKNOWN" ;
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generate
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generate
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if ( WAYS == 2 ) begin : check_hit_2ways
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if ( WAYS == 2 ) begin : check_hit_2ways
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