| Line 62... |
Line 62... |
// Control signals to execute stage
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// Control signals to execute stage
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// --------------------------------------------------
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// --------------------------------------------------
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output reg [31:0] o_imm32 = 'd0,
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output reg [31:0] o_imm32 = 'd0,
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output reg [4:0] o_imm_shift_amount = 'd0,
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output reg [4:0] o_imm_shift_amount = 'd0,
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output reg o_shift_imm_zero = 'd0,
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output reg o_shift_imm_zero = 'd0,
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output reg [3:0] o_condition = 4'he, // 4'he = al
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output wire [3:0] o_condition,
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output reg o_decode_exclusive = 'd0, // exclusive access request ( swap instruction )
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output reg o_decode_exclusive = 'd0, // exclusive access request ( swap instruction )
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output reg o_decode_iaccess = 1'd1, // Indicates an instruction access
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output wire o_decode_iaccess, // Indicates an instruction access
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output reg o_decode_daccess = 'd0, // Indicates a data access
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output reg o_decode_daccess = 'd0, // Indicates a data access
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output reg [1:0] o_status_bits_mode = 2'b11, // SVC
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output wire [1:0] o_status_bits_mode,
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output reg o_status_bits_irq_mask = 1'd1,
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output wire o_status_bits_irq_mask,
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output reg o_status_bits_firq_mask = 1'd1,
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output wire o_status_bits_firq_mask,
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|
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output reg [3:0] o_rm_sel = 'd0,
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output reg [3:0] o_rm_sel = 'd0,
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output reg [3:0] o_rs_sel = 'd0,
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output reg [3:0] o_rs_sel = 'd0,
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output reg [7:0] o_load_rd = 'd0, // [7] load flags with PC
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output reg [7:0] o_load_rd = 'd0, // [7] load flags with PC
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// [6] load status bits with PC
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// [6] load status bits with PC
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| Line 84... |
Line 84... |
output reg [1:0] o_barrel_shift_data_sel = 'd0,
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output reg [1:0] o_barrel_shift_data_sel = 'd0,
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output reg [1:0] o_barrel_shift_function = 'd0,
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output reg [1:0] o_barrel_shift_function = 'd0,
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output reg [8:0] o_alu_function = 'd0,
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output reg [8:0] o_alu_function = 'd0,
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output reg [1:0] o_multiply_function = 'd0,
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output reg [1:0] o_multiply_function = 'd0,
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output reg [2:0] o_interrupt_vector_sel = 'd0,
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output reg [2:0] o_interrupt_vector_sel = 'd0,
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output reg [3:0] o_iaddress_sel = 4'd2,
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output wire [3:0] o_iaddress_sel,
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output reg [3:0] o_daddress_sel = 4'd2,
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output wire [3:0] o_daddress_sel,
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output reg [2:0] o_pc_sel = 3'd2,
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output wire [2:0] o_pc_sel,
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output reg [1:0] o_byte_enable_sel = 'd0, // byte, halfword or word write
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output reg [1:0] o_byte_enable_sel = 'd0, // byte, halfword or word write
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output reg [2:0] o_status_bits_sel = 'd0,
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output reg [2:0] o_status_bits_sel = 'd0,
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output reg [2:0] o_reg_write_sel,
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output reg [2:0] o_reg_write_sel,
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output reg o_user_mode_regs_store_nxt,
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output reg o_user_mode_regs_store_nxt,
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output reg o_firq_not_user_mode,
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output reg o_firq_not_user_mode,
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output reg o_use_carry_in,
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output reg o_use_carry_in,
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|
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output reg o_write_data_wen = 'd0,
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output reg o_write_data_wen = 'd0,
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output reg o_base_address_wen = 'd0, // save ldm base address register
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output reg o_base_address_wen = 'd0, // save ldm base address register
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// in case of data abort
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// in case of data abort
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output reg o_pc_wen = 1'd1,
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output wire o_pc_wen,
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output reg [14:0] o_reg_bank_wen = 'd0,
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output reg [14:0] o_reg_bank_wen = 'd0,
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output reg o_status_bits_flags_wen = 'd0,
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output reg o_status_bits_flags_wen = 'd0,
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output reg o_status_bits_mode_wen = 'd0,
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output reg o_status_bits_mode_wen = 'd0,
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output reg o_status_bits_irq_mask_wen = 'd0,
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output reg o_status_bits_irq_mask_wen = 'd0,
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output reg o_status_bits_firq_mask_wen = 'd0,
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output reg o_status_bits_firq_mask_wen = 'd0,
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| Line 339... |
Line 339... |
reg rn_conflict1_r = 'd0;
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reg rn_conflict1_r = 'd0;
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reg rm_conflict1_r = 'd0;
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reg rm_conflict1_r = 'd0;
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reg rs_conflict1_r = 'd0;
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reg rs_conflict1_r = 'd0;
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reg rd_conflict1_r = 'd0;
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reg rd_conflict1_r = 'd0;
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|
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// ========================================================
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// registers for output ports with non-zero initial values
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// ========================================================
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reg [3:0] condition_r = 4'he; // 4'he = al
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reg decode_iaccess_r = 1'd1; // Indicates an instruction access
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reg [1:0] status_bits_mode_r = 2'b11; // SVC
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reg status_bits_irq_mask_r = 1'd1;
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reg status_bits_firq_mask_r = 1'd1;
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reg [3:0] iaddress_sel_r = 4'd2;
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reg [3:0] daddress_sel_r = 4'd2;
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reg [2:0] pc_sel_r = 3'd2;
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reg pc_wen_r = 1'd1;
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assign o_condition = condition_r;
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assign o_decode_iaccess = decode_iaccess_r;
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assign o_status_bits_mode = status_bits_mode_r;
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assign o_status_bits_irq_mask = status_bits_irq_mask_r;
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assign o_status_bits_firq_mask = status_bits_firq_mask_r;
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assign o_iaddress_sel = iaddress_sel_r;
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assign o_daddress_sel = daddress_sel_r;
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assign o_pc_sel = pc_sel_r;
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assign o_pc_wen = pc_wen_r;
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// ========================================================
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// ========================================================
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// Instruction Abort and Data Abort outputs
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// Instruction Abort and Data Abort outputs
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// ========================================================
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// ========================================================
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|
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assign o_iabt_trigger = instruction_iabt && o_status_bits_mode == SVC && control_state == INT_WAIT1;
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assign o_iabt_trigger = instruction_iabt && status_bits_mode_r == SVC && control_state == INT_WAIT1;
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assign o_iabt_address = instruction_address;
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assign o_iabt_address = instruction_address;
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assign o_iabt_status = instruction_iabt_status;
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assign o_iabt_status = instruction_iabt_status;
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assign o_dabt_trigger = dabt_reg && !dabt_reg_d1;
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assign o_dabt_trigger = dabt_reg && !dabt_reg_d1;
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assign o_dabt_address = fetch_address_r;
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assign o_dabt_address = fetch_address_r;
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| Line 732... |
Line 757... |
always @*
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always @*
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begin
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begin
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// default mode
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// default mode
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status_bits_mode_nxt = i_execute_status_bits[1:0]; // change to mode in execute stage get reflected
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status_bits_mode_nxt = i_execute_status_bits[1:0]; // change to mode in execute stage get reflected
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// back to this stage automatically
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// back to this stage automatically
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status_bits_irq_mask_nxt = o_status_bits_irq_mask;
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status_bits_irq_mask_nxt = status_bits_irq_mask_r;
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status_bits_firq_mask_nxt = o_status_bits_firq_mask;
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status_bits_firq_mask_nxt = status_bits_firq_mask_r;
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decode_exclusive_nxt = 1'd0;
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decode_exclusive_nxt = 1'd0;
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decode_daccess_nxt = 1'd0;
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decode_daccess_nxt = 1'd0;
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decode_iaccess_nxt = 1'd1;
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decode_iaccess_nxt = 1'd1;
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copro_operation_nxt = 'd0;
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copro_operation_nxt = 'd0;
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| Line 1426... |
Line 1451... |
// creates a 1 cycle gap with the old mode
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// creates a 1 cycle gap with the old mode
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// coming back from execute into instruction_decode
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// coming back from execute into instruction_decode
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// So squash that old mode value during this
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// So squash that old mode value during this
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// cycle of the interrupt transition
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// cycle of the interrupt transition
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if ( control_state == INT_WAIT1 )
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if ( control_state == INT_WAIT1 )
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status_bits_mode_nxt = o_status_bits_mode; // Supervisor mode
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status_bits_mode_nxt = status_bits_mode_r; // Supervisor mode
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|
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end
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end
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// Speed up the long path from u_decode/fetch_instruction_r to u_register_bank/r8_firq
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// Speed up the long path from u_decode/fetch_instruction_r to u_register_bank/r8_firq
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| Line 1441... |
Line 1466... |
// ========================================================
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// ========================================================
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// Next State Logic
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// Next State Logic
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// ========================================================
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// ========================================================
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// this replicates the current value of the execute signal in the execute stage
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// this replicates the current value of the execute signal in the execute stage
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assign instruction_execute = conditional_execute ( o_condition, i_execute_status_bits[31:28] );
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assign instruction_execute = conditional_execute ( condition_r, i_execute_status_bits[31:28] );
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// First state of executing a new instruction
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// First state of executing a new instruction
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// Its complex because of conditional execution of multi-cycle instructions
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// Its complex because of conditional execution of multi-cycle instructions
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assign instruction_valid = ((control_state == EXECUTE || control_state == PRE_FETCH_EXEC) ||
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assign instruction_valid = ((control_state == EXECUTE || control_state == PRE_FETCH_EXEC) ||
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| Line 1593... |
Line 1618... |
iabt_reg <= i_iabt;
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iabt_reg <= i_iabt;
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adex_reg <= i_adex;
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adex_reg <= i_adex;
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abt_status_reg <= i_abt_status;
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abt_status_reg <= i_abt_status;
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end
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end
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o_status_bits_mode <= status_bits_mode_nxt;
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status_bits_mode_r <= status_bits_mode_nxt;
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o_status_bits_irq_mask <= status_bits_irq_mask_nxt;
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status_bits_irq_mask_r <= status_bits_irq_mask_nxt;
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o_status_bits_firq_mask <= status_bits_firq_mask_nxt;
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status_bits_firq_mask_r <= status_bits_firq_mask_nxt;
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o_imm32 <= imm32_nxt;
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o_imm32 <= imm32_nxt;
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o_imm_shift_amount <= imm_shift_amount_nxt;
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o_imm_shift_amount <= imm_shift_amount_nxt;
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o_shift_imm_zero <= shift_imm_zero_nxt;
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o_shift_imm_zero <= shift_imm_zero_nxt;
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// when have an interrupt, execute the interrupt operation
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// when have an interrupt, execute the interrupt operation
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// unconditionally in the execute stage
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// unconditionally in the execute stage
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// ensures that status_bits register gets updated correctly
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// ensures that status_bits register gets updated correctly
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// Likewise when in middle of multi-cycle instructions
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// Likewise when in middle of multi-cycle instructions
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// execute them unconditionally
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// execute them unconditionally
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o_condition <= instruction_valid && !interrupt ? condition_nxt : AL;
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condition_r <= instruction_valid && !interrupt ? condition_nxt : AL;
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o_decode_exclusive <= decode_exclusive_nxt;
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o_decode_exclusive <= decode_exclusive_nxt;
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o_decode_iaccess <= decode_iaccess_nxt;
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decode_iaccess_r <= decode_iaccess_nxt;
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o_decode_daccess <= decode_daccess_nxt;
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o_decode_daccess <= decode_daccess_nxt;
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o_rm_sel <= rm_sel_nxt;
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o_rm_sel <= rm_sel_nxt;
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o_rs_sel <= rs_sel_nxt;
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o_rs_sel <= rs_sel_nxt;
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o_load_rd <= load_rd_nxt;
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o_load_rd <= load_rd_nxt;
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| Line 1623... |
Line 1648... |
o_barrel_shift_function <= barrel_shift_function_nxt;
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o_barrel_shift_function <= barrel_shift_function_nxt;
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o_alu_function <= alu_function_nxt;
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o_alu_function <= alu_function_nxt;
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o_use_carry_in <= use_carry_in_nxt;
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o_use_carry_in <= use_carry_in_nxt;
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o_multiply_function <= multiply_function_nxt;
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o_multiply_function <= multiply_function_nxt;
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o_interrupt_vector_sel <= next_interrupt;
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o_interrupt_vector_sel <= next_interrupt;
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o_iaddress_sel <= iaddress_sel_nxt;
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iaddress_sel_r <= iaddress_sel_nxt;
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o_daddress_sel <= daddress_sel_nxt;
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daddress_sel_r <= daddress_sel_nxt;
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o_pc_sel <= pc_sel_nxt;
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pc_sel_r <= pc_sel_nxt;
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o_byte_enable_sel <= byte_enable_sel_nxt;
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o_byte_enable_sel <= byte_enable_sel_nxt;
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o_status_bits_sel <= status_bits_sel_nxt;
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o_status_bits_sel <= status_bits_sel_nxt;
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o_reg_write_sel <= reg_write_sel_nxt;
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o_reg_write_sel <= reg_write_sel_nxt;
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o_firq_not_user_mode <= firq_not_user_mode_nxt;
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o_firq_not_user_mode <= firq_not_user_mode_nxt;
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o_write_data_wen <= write_data_wen_nxt;
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o_write_data_wen <= write_data_wen_nxt;
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o_base_address_wen <= base_address_wen_nxt;
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o_base_address_wen <= base_address_wen_nxt;
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o_pc_wen <= pc_wen_nxt;
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pc_wen_r <= pc_wen_nxt;
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o_reg_bank_wen <= reg_bank_wen_nxt;
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o_reg_bank_wen <= reg_bank_wen_nxt;
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o_status_bits_flags_wen <= status_bits_flags_wen_nxt;
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o_status_bits_flags_wen <= status_bits_flags_wen_nxt;
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o_status_bits_mode_wen <= status_bits_mode_wen_nxt;
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o_status_bits_mode_wen <= status_bits_mode_wen_nxt;
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o_status_bits_irq_mask_wen <= status_bits_irq_mask_wen_nxt;
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o_status_bits_irq_mask_wen <= status_bits_irq_mask_wen_nxt;
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o_status_bits_firq_mask_wen <= status_bits_firq_mask_wen_nxt;
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o_status_bits_firq_mask_wen <= status_bits_firq_mask_wen_nxt;
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| Line 1707... |
Line 1732... |
if ( !i_core_stall )
|
if ( !i_core_stall )
|
begin
|
begin
|
irq <= i_irq;
|
irq <= i_irq;
|
firq <= i_firq;
|
firq <= i_firq;
|
|
|
if ( control_state == INT_WAIT1 && o_status_bits_mode == SVC )
|
if ( control_state == INT_WAIT1 && status_bits_mode_r == SVC )
|
begin
|
begin
|
dabt_reg <= 1'd0;
|
dabt_reg <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
| Line 1739... |
Line 1764... |
.i_instruction_execute ( instruction_execute ),
|
.i_instruction_execute ( instruction_execute ),
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.i_instruction_address ( instruction_address ),
|
.i_instruction_address ( instruction_address ),
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.i_interrupt ( {3{interrupt}} & next_interrupt ),
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.i_interrupt ( {3{interrupt}} & next_interrupt ),
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.i_interrupt_state ( control_state == INT_WAIT2 ),
|
.i_interrupt_state ( control_state == INT_WAIT2 ),
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.i_instruction_undefined ( und_request ),
|
.i_instruction_undefined ( und_request ),
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.i_pc_sel ( o_pc_sel ),
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.i_pc_sel ( pc_sel_r ),
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.i_pc_wen ( o_pc_wen )
|
.i_pc_wen ( pc_wen_r ));
|
);
|
|
|
|
|
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wire [(15*8)-1:0] xCONTROL_STATE;
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wire [(15*8)-1:0] xCONTROL_STATE;
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wire [(15*8)-1:0] xMODE;
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wire [(15*8)-1:0] xMODE;
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wire [( 8*8)-1:0] xTYPE;
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wire [( 8*8)-1:0] xTYPE;
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| Line 1774... |
Line 1798... |
control_state == SWAP_WAIT1 ? "SWAP_WAIT1" :
|
control_state == SWAP_WAIT1 ? "SWAP_WAIT1" :
|
control_state == SWAP_WAIT2 ? "SWAP_WAIT2" :
|
control_state == SWAP_WAIT2 ? "SWAP_WAIT2" :
|
control_state == COPRO_WAIT ? "COPRO_WAIT" :
|
control_state == COPRO_WAIT ? "COPRO_WAIT" :
|
"UNKNOWN " ;
|
"UNKNOWN " ;
|
|
|
assign xMODE = mode_name ( o_status_bits_mode );
|
assign xMODE = mode_name ( status_bits_mode_r );
|
|
|
assign xTYPE =
|
assign xTYPE =
|
type == REGOP ? "REGOP" :
|
type == REGOP ? "REGOP" :
|
type == MULT ? "MULT" :
|
type == MULT ? "MULT" :
|
type == SWAP ? "SWAP" :
|
type == SWAP ? "SWAP" :
|
