| Line 286... |
Line 286... |
wire [4:0] mtrans_num_registers;
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wire [4:0] mtrans_num_registers;
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wire use_saved_current_instruction;
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wire use_saved_current_instruction;
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wire use_hold_instruction;
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wire use_hold_instruction;
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wire use_pre_fetch_instruction;
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wire use_pre_fetch_instruction;
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wire interrupt;
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wire interrupt;
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wire interrupt_or_conflict;
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wire [1:0] interrupt_mode;
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wire [1:0] interrupt_mode;
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wire [2:0] next_interrupt;
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wire [2:0] next_interrupt;
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reg irq = 'd0;
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reg irq = 'd0;
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reg firq = 'd0;
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reg firq = 'd0;
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wire firq_request;
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wire firq_request;
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| Line 455... |
Line 456... |
assign immediate_shift_op = instruction[25];
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assign immediate_shift_op = instruction[25];
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assign rds_use_rs = (type == REGOP && !instruction[25] && instruction[4]) ||
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assign rds_use_rs = (type == REGOP && !instruction[25] && instruction[4]) ||
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(type == MULT &&
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(type == MULT &&
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(control_state == MULT_PROC1 ||
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(control_state == MULT_PROC1 ||
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control_state == MULT_PROC2 ||
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control_state == MULT_PROC2 ||
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instruction_valid && !interrupt )) ;
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// instruction_valid && !interrupt )) ;
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// remove the '!conflict' term from the interrupt logic used here
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// to break a combinational loop
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(instruction_valid && !interrupt_or_conflict))) ;
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assign branch = type == BRANCH;
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assign branch = type == BRANCH;
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assign opcode_compare = opcode == CMP || opcode == CMN || opcode == TEQ || opcode == TST ;
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assign opcode_compare = opcode == CMP || opcode == CMN || opcode == TEQ || opcode == TST ;
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assign mem_op = type == TRANS;
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assign mem_op = type == TRANS;
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assign load_op = mem_op && instruction[20];
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assign load_op = mem_op && instruction[20];
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assign store_op = mem_op && !instruction[20];
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assign store_op = mem_op && !instruction[20];
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| Line 685... |
Line 691... |
// if the instruction is used
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// if the instruction is used
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und_request ? 3'd6 : // Undefined Instruction
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und_request ? 3'd6 : // Undefined Instruction
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swi_request ? 3'd7 : // SWI
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swi_request ? 3'd7 : // SWI
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3'd0 ; // none
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3'd0 ; // none
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// SWI and undefined instructions do not cause an interrupt in the decode
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// SWI and undefined instructions do not cause an interrupt in the decode
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// stage. They only trigger interrupts if they arfe executed, so the
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// stage. They only trigger interrupts if they arfe executed, so the
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// interrupt is triggered if the execute condition is met in the execute stage
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// interrupt is triggered if the execute condition is met in the execute stage
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assign interrupt = next_interrupt != 3'd0 &&
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assign interrupt = next_interrupt != 3'd0 &&
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next_interrupt != 3'd7 && // SWI
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next_interrupt != 3'd7 && // SWI
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next_interrupt != 3'd6 && // undefined interrupt
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next_interrupt != 3'd6 && // undefined interrupt
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!conflict ; // Wait for conflicts to resolve before
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!conflict ; // Wait for conflicts to resolve before
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// triggering int
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// triggering int
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// Added to use in rds_use_rs logic to break a combinational loop invloving
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// the conflict signal
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assign interrupt_or_conflict
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= next_interrupt != 3'd0 &&
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next_interrupt != 3'd7 && // SWI
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next_interrupt != 3'd6 ; // undefined interrupt
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assign interrupt_mode = next_interrupt == 3'd2 ? FIRQ :
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assign interrupt_mode = next_interrupt == 3'd2 ? FIRQ :
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next_interrupt == 3'd3 ? IRQ :
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next_interrupt == 3'd3 ? IRQ :
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next_interrupt == 3'd4 ? SVC :
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next_interrupt == 3'd4 ? SVC :
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next_interrupt == 3'd5 ? SVC :
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next_interrupt == 3'd5 ? SVC :
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next_interrupt == 3'd6 ? SVC :
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next_interrupt == 3'd6 ? SVC :
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next_interrupt == 3'd7 ? SVC :
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next_interrupt == 3'd7 ? SVC :
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next_interrupt == 3'd1 ? SVC :
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next_interrupt == 3'd1 ? SVC :
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USR ;
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USR ;
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// ========================================================
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// ========================================================
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// Generate control signals
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// Generate control signals
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// ========================================================
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// ========================================================
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always @*
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always @*
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begin
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begin
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