| Line 198... |
Line 198... |
wire shift_imm_zero_nxt;
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wire shift_imm_zero_nxt;
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wire [3:0] condition_nxt;
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wire [3:0] condition_nxt;
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reg decode_exclusive_nxt;
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reg decode_exclusive_nxt;
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reg decode_iaccess_nxt;
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reg decode_iaccess_nxt;
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reg decode_daccess_nxt;
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reg decode_daccess_nxt;
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wire shift_extend;
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reg [1:0] barrel_shift_function_nxt;
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reg [1:0] barrel_shift_function_nxt;
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wire [8:0] alu_function_nxt;
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wire [8:0] alu_function_nxt;
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reg [1:0] multiply_function_nxt;
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reg [1:0] multiply_function_nxt;
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reg [1:0] status_bits_mode_nxt;
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reg [1:0] status_bits_mode_nxt;
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| Line 445... |
Line 446... |
assign ldm_flags = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22];
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assign ldm_flags = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22];
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assign ldm_status_bits = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR;
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assign ldm_status_bits = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR;
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assign load_rd_byte = (type == TRANS || type == SWAP) && instruction[22];
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assign load_rd_byte = (type == TRANS || type == SWAP) && instruction[22];
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assign load_rd_nxt = {ldm_flags, ldm_status_bits, ldm_user_mode, load_rd_byte, rs_sel_nxt};
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assign load_rd_nxt = {ldm_flags, ldm_status_bits, ldm_user_mode, load_rd_byte, rs_sel_nxt};
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// this is used for RRX
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assign shift_extend = !instruction[25] && !instruction[4] && !(|instruction[11:7]) && instruction[6:5] == 2'b11;
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// MSB indicates valid dirty target register
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// MSB indicates valid dirty target register
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assign load_rd_d1_nxt = {o_decode_daccess && !o_write_data_wen, o_load_rd[3:0]};
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assign load_rd_d1_nxt = {o_decode_daccess && !o_write_data_wen, o_load_rd[3:0]};
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assign shift_imm = instruction[11:7];
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assign shift_imm = instruction[11:7];
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assign offset12 = { 20'h0, instruction[11:0]};
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assign offset12 = { 20'h0, instruction[11:0]};
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| Line 813... |
Line 816... |
status_bits_sel_nxt = 3'd5;
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status_bits_sel_nxt = 3'd5;
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if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD
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if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD
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begin
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begin
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alu_out_sel_nxt = 4'd1; // Add
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alu_out_sel_nxt = 4'd1; // Add
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use_carry_in_nxt = shift_extend;
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end
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end
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if ( opcode == ADC ) // Add with Carry
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if ( opcode == ADC ) // Add with Carry
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begin
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begin
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alu_out_sel_nxt = 4'd1; // Add
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alu_out_sel_nxt = 4'd1; // Add
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alu_cin_sel_nxt = 2'd2; // carry in from status_bits
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alu_cin_sel_nxt = 2'd2; // carry in from status_bits
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use_carry_in_nxt = 1'd1;
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use_carry_in_nxt = shift_extend;
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end
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end
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if ( opcode == SUB || opcode == CMP ) // Subtract
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if ( opcode == SUB || opcode == CMP ) // Subtract
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begin
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begin
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alu_out_sel_nxt = 4'd1; // Add
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alu_out_sel_nxt = 4'd1; // Add
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| Line 856... |
Line 860... |
begin
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begin
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alu_out_sel_nxt = 4'd1; // Add
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alu_out_sel_nxt = 4'd1; // Add
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alu_cin_sel_nxt = 2'd2; // carry in from status_bits
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alu_cin_sel_nxt = 2'd2; // carry in from status_bits
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alu_not_sel_nxt = 1'd1; // invert B
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alu_not_sel_nxt = 1'd1; // invert B
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alu_swap_sel_nxt = 1'd1; // swap A and B
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alu_swap_sel_nxt = 1'd1; // swap A and B
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use_carry_in_nxt = 1'd1;
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end
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end
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if ( opcode == AND || opcode == TST ) // Logical AND, Test (using AND operator)
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if ( opcode == AND || opcode == TST ) // Logical AND, Test (using AND operator)
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begin
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begin
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alu_out_sel_nxt = 4'd8; // AND
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alu_out_sel_nxt = 4'd8; // AND
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| Line 868... |
Line 873... |
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if ( opcode == EOR || opcode == TEQ ) // Logical Exclusive OR, Test Equivalence (using EOR operator)
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if ( opcode == EOR || opcode == TEQ ) // Logical Exclusive OR, Test Equivalence (using EOR operator)
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begin
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begin
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alu_out_sel_nxt = 4'd6; // XOR
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alu_out_sel_nxt = 4'd6; // XOR
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alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
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alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
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use_carry_in_nxt = 1'd1;
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end
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end
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if ( opcode == ORR )
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if ( opcode == ORR )
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begin
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begin
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alu_out_sel_nxt = 4'd7; // OR
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alu_out_sel_nxt = 4'd7; // OR
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alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
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alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
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use_carry_in_nxt = 1'd1;
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end
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end
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if ( opcode == BIC ) // Bit Clear (using AND & NOT operators)
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if ( opcode == BIC ) // Bit Clear (using AND & NOT operators)
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begin
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begin
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alu_out_sel_nxt = 4'd8; // AND
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alu_out_sel_nxt = 4'd8; // AND
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alu_not_sel_nxt = 1'd1; // invert B
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alu_not_sel_nxt = 1'd1; // invert B
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alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
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alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
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use_carry_in_nxt = 1'd1;
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end
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end
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if ( opcode == MOV ) // Move
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if ( opcode == MOV ) // Move
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begin
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begin
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alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
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alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
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use_carry_in_nxt = 1'd1;
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end
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end
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if ( opcode == MVN ) // Move NOT
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if ( opcode == MVN ) // Move NOT
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begin
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begin
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alu_not_sel_nxt = 1'd1; // invert B
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alu_not_sel_nxt = 1'd1; // invert B
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alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
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alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
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use_carry_in_nxt = 1'd1;
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end
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end
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end
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end
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// Load & Store instructions
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// Load & Store instructions
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if ( mem_op )
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if ( mem_op )
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