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`include "a25_config_defines.v"
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`include "a25_config_defines.v"
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module a25_decompile
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module a25_decompile
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(
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(
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input i_clk,
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input i_clk,
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input i_access_stall,
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input i_core_stall,
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input [31:0] i_instruction,
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input [31:0] i_instruction,
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input i_instruction_valid,
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input i_instruction_valid,
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input i_instruction_undefined,
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input i_instruction_undefined,
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input i_instruction_execute,
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input i_instruction_execute,
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input [2:0] i_interrupt, // non-zero value means interrupt triggered
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input [2:0] i_interrupt, // non-zero value means interrupt triggered
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Line 95... |
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// ========================================================
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// ========================================================
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// Delay instruction to Execute stage
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// Delay instruction to Execute stage
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// ========================================================
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// ========================================================
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( !i_access_stall && i_instruction_valid )
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if ( !i_core_stall && i_instruction_valid )
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begin
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begin
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execute_instruction <= i_instruction;
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execute_instruction <= i_instruction;
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execute_address <= i_instruction_address;
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execute_address <= i_instruction_address;
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execute_undefined <= i_instruction_undefined;
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execute_undefined <= i_instruction_undefined;
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execute_now <= 1'd1;
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execute_now <= 1'd1;
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Line 107... |
else
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else
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execute_now <= 1'd0;
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execute_now <= 1'd0;
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always @ ( posedge i_clk )
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always @ ( posedge i_clk )
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if ( !i_access_stall )
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if ( !i_core_stall )
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execute_valid <= i_instruction_valid;
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execute_valid <= i_instruction_valid;
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// ========================================================
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// ========================================================
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// Open File
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// Open File
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// ========================================================
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// ========================================================
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xINSTRUCTION_EXECUTE_R <= xINSTRUCTION_EXECUTE;
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xINSTRUCTION_EXECUTE_R <= xINSTRUCTION_EXECUTE;
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always @( posedge i_clk )
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always @( posedge i_clk )
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clk_count <= clk_count + 1'd1;
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clk_count <= clk_count + 1'd1;
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// =================================================================================
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// Memory Reads and Writes
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// =================================================================================
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reg [31:0] tmp_address;
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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// Data Write
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if ( get_1bit_signal(0) && !get_1bit_signal(3) )
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begin
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$fwrite(decompile_file, "%09d write addr ", clk_count);
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tmp_address = get_32bit_signal(2);
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fwrite_hex_drop_zeros(decompile_file, {tmp_address [31:2], 2'd0} );
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$fwrite(decompile_file, ", data %08h, be %h",
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get_32bit_signal(3), // u_cache.i_write_data
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get_4bit_signal (0)); // u_cache.i_byte_enable
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$fwrite(decompile_file, "\n");
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end
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// Data Read
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if ( get_1bit_signal(4) && !get_1bit_signal(1) )
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begin
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$fwrite(decompile_file, "%09d read addr ", clk_count);
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tmp_address = get_32bit_signal(5);
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fwrite_hex_drop_zeros(decompile_file, {tmp_address[31:2], 2'd0} );
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$fwrite(decompile_file, ", data %08h to ", get_32bit_signal(4));
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warmreg(get_4bit_signal(1));
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$fwrite(decompile_file, "\n");
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end
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// instruction
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if ( execute_now )
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if ( execute_now )
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begin
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begin
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// Interrupts override instructions that are just starting
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// Interrupts override instructions that are just starting
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if ( interrupt_d1 == 3'd0 || interrupt_d1 == 3'd7 )
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if ( interrupt_d1 == 3'd0 || interrupt_d1 == 3'd7 )
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Line 417... |
$fwrite( decompile_file,"%09d interrupt swi", clk_count );
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$fwrite( decompile_file,"%09d interrupt swi", clk_count );
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$fwrite( decompile_file,", return addr " );
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$fwrite( decompile_file,", return addr " );
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$fwrite( decompile_file,"%08x\n", pcf(get_reg_val(5'd21)-4'd4) );
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$fwrite( decompile_file,"%08x\n", pcf(get_reg_val(5'd21)-4'd4) );
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end
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end
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end
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end
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end
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always @( posedge i_clk )
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always @( posedge i_clk )
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if ( !i_access_stall )
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if ( !i_core_stall )
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begin
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begin
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interrupt_d1 <= i_interrupt;
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interrupt_d1 <= i_interrupt;
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// Asynchronous Interrupts
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// Asynchronous Interrupts
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if ( interrupt_d1 != 3'd0 && i_interrupt_state )
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if ( interrupt_d1 != 3'd0 && i_interrupt_state )
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Line 459... |
// Dont print a jump message for interrupts
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// Dont print a jump message for interrupts
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always @( posedge i_clk )
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always @( posedge i_clk )
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if (
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if (
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i_pc_sel != 3'd0 &&
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i_pc_sel != 3'd0 &&
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i_pc_wen &&
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i_pc_wen &&
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!i_access_stall &&
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!i_core_stall &&
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i_instruction_execute &&
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i_instruction_execute &&
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i_interrupt == 3'd0 &&
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i_interrupt == 3'd0 &&
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!execute_undefined &&
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!execute_undefined &&
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type != SWI &&
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type != SWI &&
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execute_address != get_32bit_signal(0) // Don't print jump to same address
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execute_address != get_32bit_signal(0) // Don't print jump to same address
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fwrite_hex_drop_zeros(decompile_file, pcf(get_32bit_signal(0)) ); // u_execute.pc_nxt
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fwrite_hex_drop_zeros(decompile_file, pcf(get_32bit_signal(0)) ); // u_execute.pc_nxt
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$fwrite(decompile_file,", r0 %08h, ", get_reg_val ( 5'd0 ));
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$fwrite(decompile_file,", r0 %08h, ", get_reg_val ( 5'd0 ));
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$fwrite(decompile_file,"r1 %08h\n", get_reg_val ( 5'd1 ));
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$fwrite(decompile_file,"r1 %08h\n", get_reg_val ( 5'd1 ));
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end
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end
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// =================================================================================
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// Memory Reads and Writes
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// =================================================================================
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reg [31:0] tmp_address;
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// Data access
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always @( posedge i_clk )
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begin
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// Data Write
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if ( get_1bit_signal(0) && !get_1bit_signal(3) )
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begin
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$fwrite(decompile_file, "%09d write addr ", clk_count);
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tmp_address = get_32bit_signal(2);
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fwrite_hex_drop_zeros(decompile_file, {tmp_address [31:2], 2'd0} );
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$fwrite(decompile_file, ", data %08h, be %h",
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get_32bit_signal(3), // u_cache.i_write_data
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get_4bit_signal (0)); // u_cache.i_byte_enable
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$fwrite(decompile_file, "\n");
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end
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// Data Read
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if ( get_1bit_signal(4) && !get_1bit_signal(1) )
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begin
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$fwrite(decompile_file, "%09d read addr ", clk_count);
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tmp_address = get_32bit_signal(5);
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fwrite_hex_drop_zeros(decompile_file, {tmp_address[31:2], 2'd0} );
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$fwrite(decompile_file, ", data %08h to ", get_32bit_signal(4));
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warmreg(get_4bit_signal(1));
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$fwrite(decompile_file, "\n");
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end
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end
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// =================================================================================
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// =================================================================================
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// Tasks
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// Tasks
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// =================================================================================
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// =================================================================================
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| Line 841... |
Line 842... |
begin
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begin
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case (num)
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case (num)
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3'd0: get_1bit_signal = `U_EXECUTE.o_write_enable;
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3'd0: get_1bit_signal = `U_EXECUTE.o_write_enable;
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3'd1: get_1bit_signal = `U_AMBER.mem_stall;
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3'd1: get_1bit_signal = `U_AMBER.mem_stall;
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3'd2: get_1bit_signal = `U_EXECUTE.o_daddress_valid;
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3'd2: get_1bit_signal = `U_EXECUTE.o_daddress_valid;
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3'd3: get_1bit_signal = `U_AMBER.access_stall;
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3'd3: get_1bit_signal = `U_AMBER.core_stall;
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3'd4: get_1bit_signal = `U_WB.mem_read_data_valid_r;
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3'd4: get_1bit_signal = `U_WB.mem_read_data_valid_r;
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endcase
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endcase
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end
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end
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endfunction
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endfunction
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