| Line 183... |
Line 183... |
// case of data abort
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// case of data abort
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wire [31:0] read_data_filtered1;
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wire [31:0] read_data_filtered1;
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wire [31:0] read_data_filtered;
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wire [31:0] read_data_filtered;
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wire [31:0] read_data_filtered_c;
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wire [31:0] read_data_filtered_c;
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reg [31:0] read_data_filtered_r = 'd0;
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reg [31:0] read_data_filtered_r = 'd0;
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reg [3:0] load_rd_r = 'd0;
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reg [5:0] load_rd_r = 'd0;
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wire [3:0] load_rd_c;
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wire [5:0] load_rd_c;
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wire write_enable_nxt;
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wire write_enable_nxt;
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wire daddress_valid_nxt;
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wire daddress_valid_nxt;
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wire iaddress_valid_nxt;
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wire iaddress_valid_nxt;
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wire priviledged_nxt;
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wire priviledged_nxt;
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| Line 481... |
Line 481... |
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// ========================================================
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// ========================================================
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// Use read value from data memory instead of from register
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// Use read value from data memory instead of from register
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// ========================================================
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// ========================================================
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assign rn = i_rn_use_read && i_rn_sel == load_rd_c ? read_data_filtered_c : reg_bank_rn;
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assign rn = i_rn_use_read && i_rn_sel == load_rd_c[3:0] && status_bits_mode == load_rd_c[5:4] ? read_data_filtered_c : reg_bank_rn;
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assign rm = i_rm_use_read && i_rm_sel == load_rd_c ? read_data_filtered_c : reg_bank_rm;
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assign rm = i_rm_use_read && i_rm_sel == load_rd_c[3:0] && status_bits_mode == load_rd_c[5:4] ? read_data_filtered_c : reg_bank_rm;
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assign rs = i_rs_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rs;
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assign rs = i_rs_use_read && i_rs_sel == load_rd_c[3:0] && status_bits_mode == load_rd_c[5:4] ? read_data_filtered_c : reg_bank_rs;
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assign rd = i_rd_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rd;
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assign rd = i_rd_use_read && i_rs_sel == load_rd_c[3:0] && status_bits_mode == load_rd_c[5:4] ? read_data_filtered_c : reg_bank_rd;
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always@( posedge i_clk )
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always@( posedge i_clk )
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if ( i_wb_read_data_valid )
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if ( i_wb_read_data_valid )
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begin
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begin
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read_data_filtered_r <= read_data_filtered;
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read_data_filtered_r <= read_data_filtered;
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load_rd_r <= i_wb_load_rd[3:0];
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load_rd_r <= {i_wb_load_rd[6:5], i_wb_load_rd[3:0]};
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end
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end
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assign read_data_filtered_c = i_wb_read_data_valid ? read_data_filtered : read_data_filtered_r;
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assign read_data_filtered_c = i_wb_read_data_valid ? read_data_filtered : read_data_filtered_r;
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assign load_rd_c = i_wb_read_data_valid ? i_wb_load_rd[3:0] : load_rd_r;
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// the register number and the mode
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assign load_rd_c = i_wb_read_data_valid ? {i_wb_load_rd[6:5], i_wb_load_rd[3:0]} : load_rd_r;
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// ========================================================
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// ========================================================
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// Set mode for the destination registers of a mem read
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// Set mode for the destination registers of a mem read
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// ========================================================
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// ========================================================
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