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module a25_fetch
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module a25_fetch
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(
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(
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input i_clk,
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input i_clk,
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input i_mem_stall,
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input i_mem_stall,
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input i_exec_stall,
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input i_conflict, // Decode stage stall pipeline because of an instruction conflict
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input i_conflict, // Decode stage stall pipeline because of an instruction conflict
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output o_fetch_stall, // when this is asserted all registers
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output o_fetch_stall, // when this is asserted all registers
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// in decode and exec stages are frozen
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// in decode and exec stages are frozen
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input i_system_rdy, // External system can stall core with this signal
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input i_system_rdy, // External system can stall core with this signal
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input i_cache_enable, // cache enable
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input i_cache_enable, // cache enable
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input i_cache_flush, // cache flush
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input i_cache_flush, // cache flush
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input [31:0] i_cacheable_area, // each bit corresponds to 2MB address space
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input [31:0] i_cacheable_area, // each bit corresponds to 2MB address space
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output o_wb_req,
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output o_wb_req,
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output o_wb_qword, // High for a quad-word fetch request
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output [31:0] o_wb_address,
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output [31:0] o_wb_address,
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input [31:0] i_wb_read_data,
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input [127:0] i_wb_read_data,
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input i_wb_ready
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input i_wb_ready
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);
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);
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`include "memory_configuration.v"
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`include "memory_configuration.v"
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wire core_stall;
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wire core_stall;
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wire cache_stall;
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wire cache_stall;
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wire [127:0] cache_read_data128;
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wire [31:0] cache_read_data;
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wire [31:0] cache_read_data;
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wire sel_cache;
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wire sel_cache;
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wire uncached_instruction_read;
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wire uncached_instruction_read;
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wire address_cachable;
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wire address_cachable;
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wire icache_wb_req;
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wire icache_wb_req;
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wire wait_wb;
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wire wait_wb;
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reg wb_req_r = 'd0;
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reg wb_req_r = 'd0;
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wire [31:0] wb_rdata32;
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// ======================================
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// ======================================
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// Memory Decode
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// Memory Decode
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// ======================================
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// ======================================
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assign address_cachable = in_cachable_mem( i_iaddress ) && i_cacheable_area[i_iaddress[25:21]];
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assign address_cachable = in_cachable_mem( i_iaddress ) && i_cacheable_area[i_iaddress[25:21]];
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// Don't start wishbone transfers when the cache is stalling the core
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// Don't start wishbone transfers when the cache is stalling the core
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// The cache stalls the core during its initialization sequence
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// The cache stalls the core during its initialization sequence
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assign uncached_instruction_read = !sel_cache && i_iaddress_valid && !(cache_stall);
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assign uncached_instruction_read = !sel_cache && i_iaddress_valid && !(cache_stall);
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// Return read data either from the wishbone bus or the cache
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// Return read data either from the wishbone bus or the cache
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assign cache_read_data = i_iaddress[3:2] == 2'd0 ? cache_read_data128[ 31: 0] :
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i_iaddress[3:2] == 2'd1 ? cache_read_data128[ 63:32] :
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i_iaddress[3:2] == 2'd2 ? cache_read_data128[ 95:64] :
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cache_read_data128[127:96] ;
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assign wb_rdata32 = i_iaddress[3:2] == 2'd0 ? i_wb_read_data[ 31: 0] :
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i_iaddress[3:2] == 2'd1 ? i_wb_read_data[ 63:32] :
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i_iaddress[3:2] == 2'd2 ? i_wb_read_data[ 95:64] :
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i_wb_read_data[127:96] ;
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assign o_fetch_instruction = sel_cache ? cache_read_data :
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assign o_fetch_instruction = sel_cache ? cache_read_data :
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uncached_instruction_read ? i_wb_read_data :
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uncached_instruction_read ? wb_rdata32 :
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32'hffeeddcc ;
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32'hffeeddcc ;
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// Stall the instruction decode and execute stages of the core
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// Stall the instruction decode and execute stages of the core
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// when the fetch stage needs more than 1 cycle to return the requested
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// when the fetch stage needs more than 1 cycle to return the requested
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// read data
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// read data
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assign o_fetch_stall = !i_system_rdy || wait_wb || cache_stall;
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assign o_fetch_stall = !i_system_rdy || wait_wb || cache_stall;
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assign o_wb_address = i_iaddress;
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assign o_wb_address = i_iaddress;
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assign o_wb_req = icache_wb_req || uncached_instruction_read;
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assign o_wb_req = icache_wb_req || uncached_instruction_read;
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assign o_wb_qword = icache_wb_req;
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assign wait_wb = (o_wb_req || wb_req_r) && !i_wb_ready;
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assign wait_wb = (o_wb_req || wb_req_r) && !i_wb_ready;
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always @(posedge i_clk)
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always @(posedge i_clk)
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wb_req_r <= o_wb_req && !i_wb_ready;
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wb_req_r <= o_wb_req && !i_wb_ready;
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assign core_stall = o_fetch_stall || i_mem_stall || i_conflict;
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assign core_stall = o_fetch_stall || i_mem_stall || i_exec_stall || i_conflict;
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// ======================================
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// ======================================
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// L1 Instruction Cache
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// L1 Instruction Cache
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// ======================================
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// ======================================
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a25_icache u_cache (
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a25_icache u_cache (
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.i_select ( sel_cache ),
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.i_select ( sel_cache ),
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.i_address ( i_iaddress ),
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.i_address ( i_iaddress ),
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.i_address_nxt ( i_iaddress_nxt ),
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.i_address_nxt ( i_iaddress_nxt ),
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.i_cache_enable ( i_cache_enable ),
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.i_cache_enable ( i_cache_enable ),
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.i_cache_flush ( i_cache_flush ),
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.i_cache_flush ( i_cache_flush ),
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.o_read_data ( cache_read_data ),
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.o_read_data ( cache_read_data128 ),
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.o_wb_req ( icache_wb_req ),
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.o_wb_req ( icache_wb_req ),
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.i_wb_read_data ( i_wb_read_data ),
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.i_wb_read_data ( i_wb_read_data ),
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.i_wb_ready ( i_wb_ready )
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.i_wb_ready ( i_wb_ready )
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);
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);
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