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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_icache.v] - Diff between revs 16 and 17
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// //
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// //
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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Synthesizable L1 Unified Data and Instruction Cache //
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// Synthesizable L1 Instruction Cache. //
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// Cache is 4-way, 256 line and 16 bytes per line for //
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// Cache is 2,3,4 or 8 way, 256 line and 16 bytes per line. //
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// a total of 16KB. The cache policy is write-through and //
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// a total of 16KB. The cache is read only. Writes from //
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// read allocate. For swap instructions (SWP and SWPB) the //
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// the core to through the data cache. //
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// location is evicted from the cache and read from main //
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// memory. //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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