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module a25_mem
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module a25_mem
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(
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(
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input i_clk,
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input i_clk,
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input i_fetch_stall, // Fetch stage asserting stall
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input i_fetch_stall, // Fetch stage asserting stall
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input i_exec_stall, // Execute stage asserting stall
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output o_mem_stall, // Mem stage asserting stall
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output o_mem_stall, // Mem stage asserting stall
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input [31:0] i_daddress,
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input [31:0] i_daddress,
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input i_daddress_valid,
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input i_daddress_valid,
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input [31:0] i_daddress_nxt, // un-registered version of address to the cache rams
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input [31:0] i_daddress_nxt, // un-registered version of address to the cache rams
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input [31:0] i_write_data,
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input [31:0] i_write_data,
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input i_write_enable,
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input i_write_enable,
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input i_exclusive, // high for read part of swap access
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input i_exclusive, // high for read part of swap access
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input [3:0] i_byte_enable,
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input [3:0] i_byte_enable,
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input [7:0] i_exec_load_rd, // The destination register for a load instruction
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input [8:0] i_exec_load_rd, // The destination register for a load instruction
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input i_cache_enable, // cache enable
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input i_cache_enable, // cache enable
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input i_cache_flush, // cache flush
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input i_cache_flush, // cache flush
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input [31:0] i_cacheable_area, // each bit corresponds to 2MB address space
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input [31:0] i_cacheable_area, // each bit corresponds to 2MB address space
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output [31:0] o_mem_read_data,
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output [31:0] o_mem_read_data,
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output o_mem_read_data_valid,
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output o_mem_read_data_valid,
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output [9:0] o_mem_load_rd, // The destination register for a load instruction
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output [10:0] o_mem_load_rd, // The destination register for a load instruction
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// Wishbone accesses
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// Wishbone accesses
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output o_wb_cached_req, // Cached Request
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output o_wb_cached_req, // Cached Request
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output o_wb_uncached_req, // Unached Request
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output o_wb_uncached_req, // Unached Request
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output o_wb_qword, // High for a quad-word read request
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output o_wb_qword, // High for a quad-word read request
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output o_wb_write, // Read=0, Write=1
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output o_wb_write, // Read=0, Write=1
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output [3:0] o_wb_byte_enable, // byte eable
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output [15:0] o_wb_byte_enable, // byte eable
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output [31:0] o_wb_write_data,
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output [127:0] o_wb_write_data,
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output [31:0] o_wb_address, // wb bus
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output [31:0] o_wb_address, // wb bus
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input [31:0] i_wb_read_data, // wb bus
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input [127:0] i_wb_uncached_rdata, // wb bus
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input [127:0] i_wb_cached_rdata, // wb bus
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input i_wb_cached_ready, // wishbone access complete and read data valid
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input i_wb_cached_ready, // wishbone access complete and read data valid
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input i_wb_uncached_ready // wishbone access complete and read data valid
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input i_wb_uncached_ready // wishbone access complete and read data valid
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);
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);
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`include "memory_configuration.v"
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`include "memory_configuration.v"
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reg uncached_wb_stop_r = 'd0;
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reg uncached_wb_stop_r = 'd0;
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reg cached_wb_stop_r = 'd0;
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reg cached_wb_stop_r = 'd0;
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wire daddress_valid_p; // pulse
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wire daddress_valid_p; // pulse
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reg [31:0] mem_read_data_r = 'd0;
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reg [31:0] mem_read_data_r = 'd0;
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reg mem_read_data_valid_r = 'd0;
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reg mem_read_data_valid_r = 'd0;
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reg [9:0] mem_load_rd_r = 'd0;
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reg [10:0] mem_load_rd_r = 'd0;
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wire [9:0] mem_load_rd_c;
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wire [10:0] mem_load_rd_c;
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wire [31:0] mem_read_data_c;
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wire [31:0] mem_read_data_c;
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wire mem_read_data_valid_c;
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wire mem_read_data_valid_c;
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reg mem_stall_r = 'd0;
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reg mem_stall_r = 'd0;
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wire use_mem_reg;
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wire use_mem_reg;
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reg fetch_only_stall_r = 'd0;
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reg fetch_only_stall_r = 'd0;
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wire fetch_only_stall;
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wire fetch_only_stall;
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wire void_output;
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wire void_output;
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wire wb_stop;
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wire wb_stop;
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reg daddress_valid_stop_r = 'd0;
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reg daddress_valid_stop_r = 'd0;
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wire [31:0] wb_rdata32;
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// ======================================
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// ======================================
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// Memory Decode
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// Memory Decode
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// ======================================
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// ======================================
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assign address_cachable = in_cachable_mem( i_daddress ) && i_cacheable_area[i_daddress[25:21]];
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assign address_cachable = in_cachable_mem( i_daddress ) && i_cacheable_area[i_daddress[25:21]];
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assign o_mem_load_rd = use_mem_reg ? mem_load_rd_r : mem_load_rd_c;
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assign o_mem_load_rd = use_mem_reg ? mem_load_rd_r : mem_load_rd_c;
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assign o_mem_read_data_valid = !void_output && (use_mem_reg ? mem_read_data_valid_r : mem_read_data_valid_c);
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assign o_mem_read_data_valid = !void_output && (use_mem_reg ? mem_read_data_valid_r : mem_read_data_valid_c);
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// Return read data either from the wishbone bus or the cache
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// Return read data either from the wishbone bus or the cache
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assign wb_rdata32 = i_daddress[3:2] == 2'd0 ? i_wb_uncached_rdata[ 31: 0] :
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i_daddress[3:2] == 2'd1 ? i_wb_uncached_rdata[ 63:32] :
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i_daddress[3:2] == 2'd2 ? i_wb_uncached_rdata[ 95:64] :
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i_wb_uncached_rdata[127:96] ;
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assign mem_read_data_c = sel_cache ? cache_read_data :
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assign mem_read_data_c = sel_cache ? cache_read_data :
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uncached_data_access ? i_wb_read_data :
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uncached_data_access ? wb_rdata32 :
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32'h76543210 ;
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32'h76543210 ;
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assign mem_load_rd_c = {i_daddress[1:0], i_exec_load_rd};
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assign mem_load_rd_c = {i_daddress[1:0], i_exec_load_rd};
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assign mem_read_data_valid_c = i_daddress_valid && !i_write_enable && !o_mem_stall;
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assign mem_read_data_valid_c = i_daddress_valid && !i_write_enable && !o_mem_stall;
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assign o_mem_stall = uncached_wb_wait || cache_stall;
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assign o_mem_stall = uncached_wb_wait || cache_stall;
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// Request wishbone access
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// Request wishbone access
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assign o_wb_byte_enable = i_byte_enable;
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assign o_wb_byte_enable = i_daddress[3:2] == 2'd0 ? {12'd0, i_byte_enable } :
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i_daddress[3:2] == 2'd1 ? { 8'd0, i_byte_enable, 4'd0} :
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i_daddress[3:2] == 2'd2 ? { 4'd0, i_byte_enable, 8'd0} :
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{ i_byte_enable, 12'd0} ;
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assign o_wb_write = i_write_enable;
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assign o_wb_write = i_write_enable;
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assign o_wb_address = {i_daddress[31:2], 2'd0};
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assign o_wb_address = {i_daddress[31:2], 2'd0};
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assign o_wb_write_data = i_write_data;
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assign o_wb_write_data = {4{i_write_data}};
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assign o_wb_cached_req = !cached_wb_stop_r && cached_wb_req;
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assign o_wb_cached_req = !cached_wb_stop_r && cached_wb_req;
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assign o_wb_uncached_req = !uncached_wb_stop_r && uncached_data_access_p;
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assign o_wb_uncached_req = !uncached_wb_stop_r && uncached_data_access_p;
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assign o_wb_qword = !cached_wb_stop_r && cached_wb_req && !i_write_enable;
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assign o_wb_qword = !cached_wb_stop_r && cached_wb_req && !i_write_enable;
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assign uncached_wb_wait = (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready;
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assign uncached_wb_wait = (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready;
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// L1 Data Cache
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// L1 Data Cache
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// ======================================
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// ======================================
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a25_dcache u_dcache (
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a25_dcache u_dcache (
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.i_clk ( i_clk ),
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.i_clk ( i_clk ),
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.i_fetch_stall ( i_fetch_stall ),
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.i_fetch_stall ( i_fetch_stall ),
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.i_exec_stall ( i_exec_stall ),
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.o_stall ( cache_stall ),
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.o_stall ( cache_stall ),
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.i_request ( sel_cache_p ),
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.i_request ( sel_cache_p ),
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.i_exclusive ( i_exclusive ),
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.i_exclusive ( i_exclusive ),
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.i_write_data ( i_write_data ),
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.i_write_data ( i_write_data ),
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.i_cache_enable ( i_cache_enable ),
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.i_cache_enable ( i_cache_enable ),
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.i_cache_flush ( i_cache_flush ),
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.i_cache_flush ( i_cache_flush ),
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.o_read_data ( cache_read_data ),
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.o_read_data ( cache_read_data ),
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.o_wb_req ( cached_wb_req ),
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.o_wb_cached_req ( cached_wb_req ),
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.i_wb_read_data ( i_wb_read_data ),
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.i_wb_cached_rdata ( i_wb_cached_rdata ),
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.i_wb_ready ( i_wb_cached_ready )
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.i_wb_cached_ready ( i_wb_cached_ready )
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);
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);
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endmodule
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endmodule
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