| Line 66... |
Line 66... |
output [10:0] o_mem_load_rd, // The destination register for a load instruction
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output [10:0] o_mem_load_rd, // The destination register for a load instruction
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// Wishbone accesses
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// Wishbone accesses
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output o_wb_cached_req, // Cached Request
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output o_wb_cached_req, // Cached Request
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output o_wb_uncached_req, // Unached Request
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output o_wb_uncached_req, // Unached Request
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output o_wb_qword, // High for a quad-word read request
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output o_wb_write, // Read=0, Write=1
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output o_wb_write, // Read=0, Write=1
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output [15:0] o_wb_byte_enable, // byte eable
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output [15:0] o_wb_byte_enable, // byte eable
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output [127:0] o_wb_write_data,
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output [127:0] o_wb_write_data,
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output [31:0] o_wb_address, // wb bus
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output [31:0] o_wb_address, // wb bus
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input [127:0] i_wb_uncached_rdata, // wb bus
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input [127:0] i_wb_uncached_rdata, // wb bus
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| Line 148... |
Line 147... |
assign o_wb_write = i_write_enable;
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assign o_wb_write = i_write_enable;
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assign o_wb_address = {i_daddress[31:2], 2'd0};
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assign o_wb_address = {i_daddress[31:2], 2'd0};
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assign o_wb_write_data = {4{i_write_data}};
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assign o_wb_write_data = {4{i_write_data}};
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assign o_wb_cached_req = !cached_wb_stop_r && cached_wb_req;
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assign o_wb_cached_req = !cached_wb_stop_r && cached_wb_req;
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assign o_wb_uncached_req = !uncached_wb_stop_r && uncached_data_access_p;
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assign o_wb_uncached_req = !uncached_wb_stop_r && uncached_data_access_p;
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assign o_wb_qword = !cached_wb_stop_r && cached_wb_req && !i_write_enable;
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assign uncached_wb_wait = (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready;
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assign uncached_wb_wait = (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready;
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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begin
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