| Line 112... |
Line 112... |
// Memory Decode
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// Memory Decode
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// ======================================
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// ======================================
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assign address_cachable = in_cachable_mem( i_daddress ) && i_cacheable_area[i_daddress[25:21]];
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assign address_cachable = in_cachable_mem( i_daddress ) && i_cacheable_area[i_daddress[25:21]];
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assign sel_cache_p = daddress_valid_p && address_cachable && i_cache_enable && !i_exclusive;
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assign sel_cache_p = daddress_valid_p && address_cachable && i_cache_enable && !i_exclusive;
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assign sel_cache = i_daddress_valid && address_cachable && i_cache_enable && !i_exclusive;
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assign sel_cache = i_daddress_valid && address_cachable && i_cache_enable && !i_exclusive;
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assign uncached_data_access = i_daddress_valid && !sel_cache && !(cache_stall);
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assign uncached_data_access = i_daddress_valid && !sel_cache && !cache_stall;
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assign uncached_data_access_p = daddress_valid_p && !sel_cache && !(cache_stall);
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assign uncached_data_access_p = daddress_valid_p && !sel_cache;
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assign use_mem_reg = wb_stop && !mem_stall_r;
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assign use_mem_reg = wb_stop && !mem_stall_r;
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assign o_mem_read_data = use_mem_reg ? mem_read_data_r : mem_read_data_c;
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assign o_mem_read_data = use_mem_reg ? mem_read_data_r : mem_read_data_c;
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assign o_mem_load_rd = use_mem_reg ? mem_load_rd_r : mem_load_rd_c;
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assign o_mem_load_rd = use_mem_reg ? mem_load_rd_r : mem_load_rd_c;
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assign o_mem_read_data_valid = !void_output && (use_mem_reg ? mem_read_data_valid_r : mem_read_data_valid_c);
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assign o_mem_read_data_valid = !void_output && (use_mem_reg ? mem_read_data_valid_r : mem_read_data_valid_c);
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| Line 168... |
Line 168... |
// pulse this signal
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// pulse this signal
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assign daddress_valid_p = i_daddress_valid && !daddress_valid_stop_r;
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assign daddress_valid_p = i_daddress_valid && !daddress_valid_stop_r;
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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begin
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uncached_wb_stop_r <= (uncached_wb_stop_r || uncached_data_access_p) && (i_fetch_stall || o_mem_stall);
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uncached_wb_stop_r <= (uncached_wb_stop_r || (uncached_data_access_p&&!cache_stall)) && (i_fetch_stall || o_mem_stall);
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cached_wb_stop_r <= (cached_wb_stop_r || cached_wb_req) && (i_fetch_stall || o_mem_stall);
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cached_wb_stop_r <= (cached_wb_stop_r || cached_wb_req) && (i_fetch_stall || o_mem_stall);
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daddress_valid_stop_r <= (daddress_valid_stop_r || daddress_valid_p) && (i_fetch_stall || o_mem_stall);
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daddress_valid_stop_r <= (daddress_valid_stop_r || daddress_valid_p) && (i_fetch_stall || o_mem_stall);
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// hold this until the mem access completes
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// hold this until the mem access completes
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mem_stall_r <= o_mem_stall;
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mem_stall_r <= o_mem_stall;
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end
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end
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