| Line 62... |
Line 62... |
input i_clk,
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input i_clk,
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// Port 0 - dcache uncached
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// Port 0 - dcache uncached
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input i_port0_req,
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input i_port0_req,
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output o_port0_ack,
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input i_port0_write,
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input i_port0_write,
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input [127:0] i_port0_wdata,
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input [127:0] i_port0_wdata,
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input [15:0] i_port0_be,
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input [15:0] i_port0_be,
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input [31:0] i_port0_addr,
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input [31:0] i_port0_addr,
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output [127:0] o_port0_rdata,
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output [127:0] o_port0_rdata,
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output o_port0_ready,
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// Port 1 - dcache cached
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// Port 1 - dcache cached
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input i_port1_req,
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input i_port1_req,
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output o_port1_ack,
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input i_port1_write,
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input i_port1_write,
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input [127:0] i_port1_wdata,
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input [127:0] i_port1_wdata,
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input [15:0] i_port1_be,
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input [15:0] i_port1_be,
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input [31:0] i_port1_addr,
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input [31:0] i_port1_addr,
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output [127:0] o_port1_rdata,
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output [127:0] o_port1_rdata,
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output o_port1_ready,
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// Port 2 - instruction cache accesses, read only
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// Port 2 - instruction cache accesses, read only
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input i_port2_req,
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input i_port2_req,
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output o_port2_ack,
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input i_port2_write,
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input i_port2_write,
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input [127:0] i_port2_wdata,
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input [127:0] i_port2_wdata,
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input [15:0] i_port2_be,
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input [15:0] i_port2_be,
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input [31:0] i_port2_addr,
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input [31:0] i_port2_addr,
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output [127:0] o_port2_rdata,
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output [127:0] o_port2_rdata,
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output o_port2_ready,
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// 128-bit Wishbone Bus
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// 128-bit Wishbone Bus
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output reg [31:0] o_wb_adr = 'd0,
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output reg [31:0] o_wb_adr = 'd0,
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output reg [15:0] o_wb_sel = 'd0,
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output reg [15:0] o_wb_sel = 'd0,
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| Line 128... |
Line 128... |
// ----------------------------------------------------
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// ----------------------------------------------------
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a25_wishbone_buf u_a25_wishbone_buf_p0 (
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a25_wishbone_buf u_a25_wishbone_buf_p0 (
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.i_clk ( i_clk ),
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.i_clk ( i_clk ),
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.i_req ( i_port0_req ),
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.i_req ( i_port0_req ),
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.o_ack ( o_port0_ack ),
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.i_write ( i_port0_write ),
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.i_write ( i_port0_write ),
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.i_wdata ( i_port0_wdata ),
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.i_wdata ( i_port0_wdata ),
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.i_be ( i_port0_be ),
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.i_be ( i_port0_be ),
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.i_addr ( i_port0_addr ),
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.i_addr ( i_port0_addr ),
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.o_rdata ( o_port0_rdata ),
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.o_rdata ( o_port0_rdata ),
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.o_ready ( o_port0_ready ),
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.o_valid ( wbuf_valid [0] ),
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.o_valid ( wbuf_valid [0] ),
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.i_accepted ( wbuf_accepted [0] ),
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.i_accepted ( wbuf_accepted [0] ),
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.o_write ( wbuf_write [0] ),
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.o_write ( wbuf_write [0] ),
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.o_wdata ( wbuf_wdata [0] ),
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.o_wdata ( wbuf_wdata [0] ),
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| Line 150... |
Line 150... |
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a25_wishbone_buf u_a25_wishbone_buf_p1 (
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a25_wishbone_buf u_a25_wishbone_buf_p1 (
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.i_clk ( i_clk ),
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.i_clk ( i_clk ),
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.i_req ( i_port1_req ),
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.i_req ( i_port1_req ),
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.o_ack ( o_port1_ack ),
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.i_write ( i_port1_write ),
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.i_write ( i_port1_write ),
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.i_wdata ( i_port1_wdata ),
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.i_wdata ( i_port1_wdata ),
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.i_be ( i_port1_be ),
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.i_be ( i_port1_be ),
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.i_addr ( i_port1_addr ),
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.i_addr ( i_port1_addr ),
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.o_rdata ( o_port1_rdata ),
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.o_rdata ( o_port1_rdata ),
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.o_ready ( o_port1_ready ),
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.o_valid ( wbuf_valid [1] ),
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.o_valid ( wbuf_valid [1] ),
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.i_accepted ( wbuf_accepted [1] ),
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.i_accepted ( wbuf_accepted [1] ),
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.o_write ( wbuf_write [1] ),
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.o_write ( wbuf_write [1] ),
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.o_wdata ( wbuf_wdata [1] ),
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.o_wdata ( wbuf_wdata [1] ),
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| Line 172... |
Line 172... |
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a25_wishbone_buf u_a25_wishbone_buf_p2 (
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a25_wishbone_buf u_a25_wishbone_buf_p2 (
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.i_clk ( i_clk ),
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.i_clk ( i_clk ),
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.i_req ( i_port2_req ),
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.i_req ( i_port2_req ),
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.o_ack ( o_port2_ack ),
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.i_write ( i_port2_write ),
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.i_write ( i_port2_write ),
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.i_wdata ( i_port2_wdata ),
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.i_wdata ( i_port2_wdata ),
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.i_be ( i_port2_be ),
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.i_be ( i_port2_be ),
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.i_addr ( i_port2_addr ),
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.i_addr ( i_port2_addr ),
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.o_rdata ( o_port2_rdata ),
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.o_rdata ( o_port2_rdata ),
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.o_ready ( o_port2_ready ),
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.o_valid ( wbuf_valid [2] ),
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.o_valid ( wbuf_valid [2] ),
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.i_accepted ( wbuf_accepted [2] ),
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.i_accepted ( wbuf_accepted [2] ),
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.o_write ( wbuf_write [2] ),
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.o_write ( wbuf_write [2] ),
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.o_wdata ( wbuf_wdata [2] ),
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.o_wdata ( wbuf_wdata [2] ),
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