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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_wishbone_buf.v] - Diff between revs 36 and 39

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Rev 36 Rev 39
Line 57... Line 57...
input                       i_write,
input                       i_write,
input       [127:0]         i_wdata,
input       [127:0]         i_wdata,
input       [15:0]          i_be,
input       [15:0]          i_be,
input       [31:0]          i_addr,
input       [31:0]          i_addr,
output      [127:0]         o_rdata,
output      [127:0]         o_rdata,
output                      o_ready,
output                      o_ack,
 
 
// Wishbone side
// Wishbone side
output                      o_valid,
output                      o_valid,
input                       i_accepted,
input                       i_accepted,
output                      o_write,
output                      o_write,
Line 74... Line 74...
 
 
 
 
// ----------------------------------------------------
// ----------------------------------------------------
// Signals
// Signals
// ----------------------------------------------------
// ----------------------------------------------------
reg                         wbuf_used_r = 'd0;
reg  [1:0]                  wbuf_used_r     = 'd0;
reg  [127:0]                wbuf_wdata_r;
reg  [127:0]                wbuf_wdata_r    [1:0];
reg  [31:0]                 wbuf_addr_r;
reg  [31:0]                 wbuf_addr_r     [1:0];
reg  [15:0]                 wbuf_be_r;
reg  [15:0]                 wbuf_be_r       [1:0];
reg                         wbuf_write_r = 'd0;
reg  [1:0]                  wbuf_write_r    = 'd0;
wire                        in_wreq = i_req && i_write;
reg                         wbuf_wp_r       = 'd0;        // write buf write pointer
 
reg                         wbuf_rp_r       = 'd0;        // write buf read pointer
reg                         busy_reading_r = 'd0;
reg                         busy_reading_r = 'd0;
 
reg                         wait_rdata_valid_r = 'd0;
 
wire                        in_wreq;
 
reg                         ack_owed_r      = 'd0;
 
 
// ----------------------------------------------------
// ----------------------------------------------------
// Access Buffer
// Access Buffer
// ----------------------------------------------------
// ----------------------------------------------------
 
assign in_wreq = i_req && i_write;
 
assign push    = i_req && !busy_reading_r && (wbuf_used_r == 2'd1 || (wbuf_used_r == 2'd0 && !i_accepted));
 
assign pop     = o_valid && i_accepted && wbuf_used_r != 2'd0;
 
 
always @(posedge i_clk)
always @(posedge i_clk)
    if (i_req && !wbuf_used_r)
    if (push && pop)
        begin
        wbuf_used_r     <= wbuf_used_r;
        wbuf_used_r     <= !i_accepted;
    else if (push)
        wbuf_wdata_r    <= i_wdata;
        wbuf_used_r     <= wbuf_used_r + 1'd1;
        wbuf_addr_r     <= i_addr;
    else if (pop)
        wbuf_be_r       <= i_write ? i_be : 16'hffff;
        wbuf_used_r     <= wbuf_used_r - 1'd1;
        wbuf_write_r    <= i_write;
 
        end
always @(posedge i_clk)
    else if ( i_req && wbuf_used_r && o_valid && i_accepted)
    if (push && in_wreq && !o_ack)
 
        ack_owed_r = 1'd1;
 
    else if (!i_req && o_ack)
 
        ack_owed_r = 1'd0;
 
 
 
always @(posedge i_clk)
 
    if (push)
        begin
        begin
        wbuf_used_r     <= 1'd1;
        wbuf_wdata_r [wbuf_wp_r]   <= i_wdata;
        wbuf_wdata_r    <= i_wdata;
        wbuf_addr_r  [wbuf_wp_r]   <= i_addr;
        wbuf_addr_r     <= i_addr;
        wbuf_be_r    [wbuf_wp_r]   <= i_write ? i_be : 16'hffff;
        wbuf_be_r       <= i_write ? i_be : 16'hffff;
        wbuf_write_r [wbuf_wp_r]   <= i_write;
        wbuf_write_r    <= i_write;
        wbuf_wp_r                  <= !wbuf_wp_r;
        end
        end
    else if (o_valid && i_accepted && wbuf_write_r)
 
        wbuf_used_r     <= 1'd0;
always @(posedge i_clk)
    else if (i_rdata_valid && !wbuf_write_r)
    if (pop)
        wbuf_used_r     <= 1'd0;
        wbuf_rp_r                  <= !wbuf_rp_r;
 
 
 
 
// ----------------------------------------------------
// ----------------------------------------------------
// Output logic
// Output logic
// ----------------------------------------------------
// ----------------------------------------------------
assign o_wdata = wbuf_used_r ? wbuf_wdata_r : i_wdata;
assign o_wdata = wbuf_used_r != 2'd0 ? wbuf_wdata_r[wbuf_rp_r] : i_wdata;
assign o_write = wbuf_used_r ? wbuf_write_r : i_write;
assign o_write = wbuf_used_r != 2'd0 ? wbuf_write_r[wbuf_rp_r] : i_write;
assign o_addr  = wbuf_used_r ? wbuf_addr_r  : i_addr;
assign o_addr  = wbuf_used_r != 2'd0 ? wbuf_addr_r [wbuf_rp_r] : i_addr;
assign o_be    = wbuf_used_r ? wbuf_be_r    : i_write ? i_be : 16'hffff;
assign o_be    = wbuf_used_r != 2'd0 ? wbuf_be_r   [wbuf_rp_r] : i_write ? i_be : 16'hffff;
 
 
assign o_valid   = (wbuf_used_r || i_req) && !busy_reading_r;
assign o_ack   = (in_wreq ? (wbuf_used_r == 2'd0) : i_rdata_valid) || (ack_owed_r && pop);
 
assign o_valid = (wbuf_used_r != 2'd0 || i_req) && !wait_rdata_valid_r;
 
 
assign o_rdata = i_rdata;
assign o_rdata = i_rdata;
assign o_ready = in_wreq ? (!wbuf_used_r || i_accepted) : i_rdata_valid;
 
 
 
 
 
always@(posedge i_clk)
always@(posedge i_clk)
    if (o_valid && !o_write && i_accepted)
    if (o_valid && !o_write)
        busy_reading_r <= 1'd1;
        busy_reading_r <= 1'd1;
    else if (i_rdata_valid)
    else if (i_rdata_valid)
        busy_reading_r <= 1'd0;
        busy_reading_r <= 1'd0;
 
 
 
always@(posedge i_clk)
 
    if (o_valid && !o_write && i_accepted)
 
        wait_rdata_valid_r <= 1'd1;
 
    else if (i_rdata_valid)
 
        wait_rdata_valid_r <= 1'd0;
endmodule
endmodule
 
 
 
 
 
 
 
 

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